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2, 31.76 w, digital input, filterless stereo clas s-d audio amplifier data sheet SSM3582 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features digital input stereo, high efficiency class-d amplifier operates from a single 4.5 v to 16 v supply state-of-the-art, proprietary, filterless - modulation 106.5 db signal-to-noise ratio 0.004% total harmonic distortion plus noise (thd + n) at 5 w into 8 38.5 v rms a weighted output noise pop/clickless on/off sequence 2 14.67 w output at 12 v supply to 4 loads at <1% thd + n 2 14.4 w output at 16 v supply to 8 loads at <1% thd + n mono mode for increased maximum output power 1 49.69 w output at 16 v supply to 2 loads at <1% thd + n support for low impedance loads as low as 3 /5 h in stereo mode as low as 2 /5 h in mono mode high power efficiency 93.8% efficiency into an 8 load 90.6% efficiency into a 4 load 12.34 ma quiescent current with single 12 v pv dd supply single supply operation with internal ldos or option to use an external 5 v and 1.8 v supply for lowest power consumption i 2 c control and hardware modes wi th up to 16 pin-selectable slots/addresses supported sample rates from 8 khz to 192 khz; 24-bit resolution multiple pcm audio serial data formats tdm slave with support for up to 16 devices on a single bus i 2 s or left justified slave adjustable full-scale output tailored for many pvdd sources 2- and 3-cell li-ion batteries digital volume control with selectable smooth ramp automatic power-down function supply monitoring automatic gain control (agc) function reduces system brownout standalone operational mode without i 2 c temperature sensor with 1c step readout via i 2 c short-circuit, undervoltage, and thermal protection thermal early warning power-on reset pv dd sensing adc 40-lead, 6 mm 6 mm lfcsp with thermal pad applications mobile computing all in one computers portable electronics wireless speakers televisions functional block diagram outl+ outl? sda scl a ddr0 a ddr1 pvdd dvdd agnd bstl+ bstl? pgnd dac pvdd adc temperature sensor dvdd 1.8v ldo volume battery agc SSM3582 three-level - ? modulator full bridge power stage 13399-001 i 2 c control i 2 s tdm interface blck fsync sdat a outr+ outr? bstr+ bstr? dac three-level - ? modulator full bridge power stage dvdd_en a vdd avdd 5v ldo a vdd_en figure 1.
SSM3582 data sheet rev. 0| page 2 of 59 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? general description ......................................................................... 3 ? specifications ..................................................................................... 4 ? digital input/output specifications........................................... 8 ? digital timing specifications ..................................................... 8 ? digital input timing specifications ........................................... 8 ? absolute maximum ratings .......................................................... 11 ? thermal resistance .................................................................... 11 ? esd caution ................................................................................ 11 ? pin configuration and function descriptions ........................... 12 ? typical performance characteristics ........................................... 14 ? theory of operation ...................................................................... 25 ? overview ...................................................................................... 25 ? power supplies ............................................................................ 25 ? power-up sequence ................................................................... 26 ? power-down operation ............................................................ 26 ? clocking ....................................................................................... 26 ? digital audio serial interface ................................................... 26 ? standalone operation ................................................................ 30 ? mono mode ................................................................................. 31 ? analog and digital gain ........................................................... 31 ? pop and click suppression ........................................................ 31 ? temperature sensor ................................................................... 31 ? faults and limiter status reporting ........................................ 32 ? vbat (pv dd ) sensing ................................................................ 32 ? limiter and battery tracking threshold control .................. 32 ? high frequency clipper ............................................................ 35 ? emi noise .................................................................................... 35 ? output modulation description .............................................. 35 ? bootstrap capacitors.................................................................. 36 ? power supply decoupling ......................................................... 36 ? output emi filtering ................................................................. 36 ? pcb placement ........................................................................... 36 ? layout .......................................................................................... 37 ? register summary .......................................................................... 38 ? register details ............................................................................... 39 ? typical application circuit ........................................................... 57 ? outline dimensions ....................................................................... 59 ? ordering guide .......................................................................... 59 ? revision history 4/16revision 0: initial version
data sheet SSM3582 rev. 0| page 3 of 59 general description the SSM3582 is a fully integrated, high efficiency, digital input stereo class-d audio amplifier. it can operate from a single supply, and requires only a few external components, significantly reducing the circuit bill of materials. a proprietary, spread spectrum - modulation scheme enables direct connection to the speaker, and ensures state-of- the-art analog performance while lowering radiated emissions compared to other class-d architectures. an optional ultralow electromagnetic interference (emi) mode significantly reduces radiated emissions above 100 mhz, enabling longer speaker cable lengths. audio is transmitted digitally to the amplifier, minimizing the possibility of signal corruption in digital environments. the amplifier provides outstanding analog performance, with an over 106 db signal-to-noise ratio and a vanishingly low 0.004% thd + n. the SSM3582 operates from a single 4.5 v to 16 v supply, and is capable of delivering 2 15 w rms continuously into 8 and 4 loads at <1% total harmonic distortion (thd). the efficient modulation scheme maintains excellent power efficiency over a wide range of impedances: 93% into an 8 load and 90% into a 4 load. optimization of the output pulse maintains performance at impedances as low as 3 /5 h, enabling its use with extended bandwidth tweeters. the pulse code modulation (pcm) audio serial port supports most common protocols, such as i 2 s, left justified, and time division multiplexing (tdm), and can address up to 16 devices on a single interface, for up to 32 audio playback channels. ic operation is controlled through a dedicated i 2 c interface. the two addrx pins (2, 5-level) define up to 16 individual addresses in i 2 c and standalone modes, and automatically set the default tdm slots attribution. a micropower shutdown mode is triggered by removing the digital audio interface clock, with a typical current of <1 a. a software power-down mode is also available. an automatic power-down feature shuts down the amplifier and the digital-to-analog converter (dac) when no signal is present at the input, minimizing power consumption during digital silence. the device restarts when nonzero data is present at the input. mute and unmute transitions are pop/click free. the SSM3582 is specified over the commercial temperature range of ?40 ? c to +85 ? c. the device has built-in thermal shutdown and output short-circuit protection, as well as an early thermal warning with programmable gain limiting to maintain operation. the SSM3582 is available in a 40-lead, 6 mm 6 mm lead frame chip scale package (lfcsp), with a thermal pad to improve heat dissipation.
SSM3582 data sheet rev. 0| page 4 of 59 specifications pv dd = 12 v, av dd = 5 v (external), dv dd = 1.8 v (external), r l = 8 + 33 h, bclk = 3.072 mhz, fsync = 48 khz, t a = ?40c to +85c, unless otherwise noted. the measurements are taken with a 20 khz aes17 low-pass filter. the other load impedances used a re 4 + 15 h and 3 + 10 h. measurements are taken with a 20 khz aes17 low-pass filter, unless otherwise noted. table 1. parameter symbol test conditions/comments min typ max unit device characteristics output power per channel p o stereo mode f = 1 khz, both channels driven r l = 8 , thd + n < 1%, f = 1 khz, 20 khz bw, pv dd = 16 v 14.4 w r l = 8 , thd + n < 1%, f = 1 khz, 20 khz bw, pv dd = 12 v 8.1 w r l = 8 , thd + n < 1%, f = 1 khz, 20 khz bw, pv dd = 7 v 2.76 w r l = 8 , thd + n < 1%, f = 1 khz, 20 khz bw, pv dd = 5 v 1.41 w r l = 8 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 16 v 18 w r l = 8 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 12 v 10 w r l = 8 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 7 v 3.43 w r l = 8 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 5 v 1.75 w r l = 4 , thd + n < 1%, f = 1 khz, 20 khz bw, pv dd = 16 v 25.6 w r l = 4 , thd + n < 1%, f = 1 khz, 20 khz bw, pv dd = 12 v 14.67 w r l = 4 , thd + n < 1%, f = 1 khz, 20 khz bw, pv dd = 7 v 5.06 w r l = 4 , thd +n < 1%, f = 1 khz, 20 khz bw, pv dd = 5 v 2.6 w r l = 4 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 16 v 31.76 w r l = 4 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 12 v 18.31 w r l = 4 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 7 v 6.3 w r l = 4 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 5 v 3.21 w mono mode f = 1 khz r l = 3 , thd +n < 1%, f = 1 khz, 20 khz bw, pv dd = 16 v 36.11 w r l = 3 , thd +n < 1%, f = 1 khz, 20 khz bw, pv dd = 12 v 20.46 w r l = 3 , thd +n < 1%, f = 1 khz, 20 khz bw, pv dd = 7 v 7 w r l = 3 , thd +n < 1%, f = 1 khz, 20 khz bw, pv dd = 5 v 3.58 w r l = 3 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 16 v 44.96 w r l = 3 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 12 v 25.49 w r l = 3 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 7 v 8.7 w r l = 3 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 5 v 4.43 w r l = 2 , thd + n < 1%, f = 1 khz, 20 khz bw, pv dd = 16 v 49.69 w r l = 2 , thd +n < 1%, f = 1 khz, 20 khz bw, pv dd = 12 v 28.55 w r l = 2 , thd +n < 1%, f = 1 khz, 20 khz bw, pv dd = 7 v 9.85 w r l = 2 , thd +n < 1%, f = 1 khz, 20 khz bw, pv dd = 5 v 5 w r l = 2 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 16 v 62.4 w r l = 2 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 12 v 35.5 w r l = 2 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 7 v 12.22 w r l = 2 , thd + n = 10%, f = 1 khz, 20 khz bw, pv dd = 5 v 6.22 w minimal load inductance speaker inductance 5 h efficiency stereo mode both channels driven p o = 10 w, r l = 8 , pv dd = 12 v 94 % p o = 10 w, r l = 8 , pv dd = 12 v (low emi mode) 93.8 % p o = 18 w, r l = 4 , pv dd = 12 v 90.6 % p o = 15 w, r l = 4 , pv dd = 12 v (low emi mode) 89.5 % mono mode p o = 25 w, r l = 3 , pv dd = 12 v 92.3 % p o = 25 w, r l = 3 , pv dd = 12 v (low emi mode) 92.1 % p o = 35 w, r l = 2 , pv dd = 12 v 89.9 % p o = 35 w, r l = 2 , pv dd = 12 v (low emi mode) 89.7 %
data sheet SSM3582 rev. 0| page 5 of 59 parameter symbol test conditions/comments min typ max unit total harmonic distortion + noise thd + n p o = 5 w into 8 , f = 1 khz, pv dd = 12 v 0.004 % output stage on resistance r on 100 m overcurrent protection trip point i oc 6 a peak average switching frequency f sw 300 khz differential output offset voltage v oos a v = 19 db 1 mv crosstalk between left and right measured at 1 khz with regards to full-scale output 100 db power supplies supply voltage range pv dd 4.5 16 v av dd 4.5 5.0 5.5 v dv dd 1.62 1.8 1.98 v power supply rejection ratio psrr ac psrr ac v ripple =100 mv rms at 1 khz 86 db v ripple =1 v rms at 1 khz 88 db analog gain a v measured with 0 dbfs input at 1 khz gain = 00 pv dd 6.3 v 6.2 v peak gain = 01 pv dd 9 v 8.75 v peak gain = 10 pv dd 12.6 v 12.5 v peak gain = 11 pv dd = 16 v 15.5 v peak shutdown control 1 turn on time, volume ramp disabled t wu time from spwdn = 0 to output switching, dac_hv = 1 or dac_mute_x = 1, t wu = 4 fsync cycles to 7 fsync cycles + 7.68 ms f s = 12 khz 8.01 8.27 ms f s = 24 khz 7.84 7.98 ms f s = 48 khz 7.76 7.83 ms f s = 96 khz 7.72 7.76 ms f s = 192 khz 7.70 7.72 ms turn on time, volume ramp enabled t wur time from spwdn = 0 to full volume output switching, dac_hv = 0 and dac_mute_x = 0, vol_x = 0x40 f s = 12 khz t wur = t wu + 15.83 ms 23.84 24.10 ms f s = 24 khz t wur = t wu + 15.83 ms 23.67 23.81 ms f s = 48 khz t wur = t wu + 15.83 ms 23.59 23.66 ms f s = 96 khz t wur = t wu + 7.92 ms 15.64 15.68 ms f s = 192 khz t wur = t wu + 0.99 ms 8.69 8.71 ms turn off time, volume ramp disabled t sd time from spwdn = 1 to full power-down, dac_hv = 1 or dac_mute_x = 1 100 s turn off time, volume ramp enabled t sdr time from spwdn = 1 to full power-down, dac_hv = 0 and dac_mute_x = 0, vol_x = 0x40 f s = 12 khz t sdr = t sd + 15.83 ms 15.932 ms f s = 24 khz t sdr = t sd + 15.83 ms 15.932 ms f s = 48 khz t sdr = t sd + 15.83 ms 15.932 ms f s = 96 khz t sdr = t sd + 7.92 ms 8.016 ms f s = 192 khz t sdr = t sd + 0.99 ms 1.09 ms output impedance z out 100 k
SSM3582 data sheet rev. 0| page 6 of 59 parameter symbol test conditions/comments min typ max unit noise performance 2 stereo mode output voltage noise e n f = 20 hz to 20 khz, a weighted, pv dd = 12 v, 8 37.8 v rms f = 20 hz to 20 khz, a weighted, pv dd = 16 v, 8 38.5 v rms f = 20 hz to 20 khz, a weighted, pv dd = 12 v, 4 36.8 v rms f = 20 hz to 20 khz, a weighted, pv dd = 16 v, 4 36.3 v rms signal-to-noise ratio snr p o = 8.1 w, r l = 8 , a v = 19 db, pv dd = 12 v, a weighted 106.5 db p o = 14.4 w, r l = 8 , a v = 21 db, pv dd = 16 v, a weighted 108.9 db p o = 14.67 w, r l = 4 , a v = 19 db, pv dd = 12 v, a weighted 106.3 db p o = 25.58 w, r l = 4 , a v = 21 db, pv dd = 16 v, a weighted 108.9 db pv dd adc performance pv dd sense full-scale range pv dd with full-scale adc output 3.8 16.2 v pv dd sense absolute accuracy pv dd = 15 v ?8 +8 lsb pv dd = 5 v ?6 +6 lsb resolution unsigned 8-bit outp ut with 3.8 v offset 8 bits temperature sense adc temperature sense range ?60 +160 c temperature sense accuracy 5 c die temperature overtemperature warning 117 c overtemperature protection 145 c undervoltage fault av dd 3.6 v pv dd 3.6 v 1 guaranteed by design. 2 noise performance is based on the bench data for t a = ?40c to +85c. software master power-down indicates that the clocks are turned off. automatic power-down indicates that there is no dither or zero input signal with clocks on; the device enters soft power-down after 2048 cycles of zero input values. quiescent indicates tria ngular dither with zero input signal. all specifications are typical, with a 48 khz sample rate, in stereo mode, unless otherwise noted. table 2. power supply current consumption, no load 1 edge rate control mode internal regulator i pvdd i dvdd i avdd test conditions pv dd = 5 v pv dd = 12 v pv dd = 16 v pv dd = 1.8 v pv dd = 5 v unit normal disabled software master power-down 0.065 0.065 0.065 2.68 7.542 a automatic power-down 0.065 0.065 0.065 43.72 7.542 a quiescent 2.54 4.94 6.25 0.945 6.335 ma enabled software master power-down 0.065 0.065 0.065 n/a n/a a automatic power-down 209 286 329 n/a n/a a quiescent 9.78 12.38 14.05 n/a n/a ma low emi disabled software master power-down 0.065 0.065 0.065 2.68 7.542 a automatic power-down 0.065 0.065 0.065 43.72 7.542 a quiescent 2.56 5.01 6.31 0.945 6.171 ma enabled software master power-down 0.065 0.065 0.065 n/a n/a a automatic power-down 209 286 329 n/a n/a a quiescent 9.69 12.09 13.74 n/a n/a ma 1 n/a means not applicable.
data sheet SSM3582 rev. 0| page 7 of 59 table 3. power supply current consumption, 4 + 15 h 1 edge rate control mode internal regulator i pvdd i dvdd i avdd test conditions pv dd = 5 v pv dd = 12 v pv dd = 16 v pv dd = 1.8 v pv dd = 5 v unit normal disabled software master power-down 0.065 0.065 0.065 2.68 7.542 a automatic power-down 0.065 0.065 0.065 43.72 7.542 a quiescent 2.6 4.93 6.25 0.945 6.477 ma enabled software master power-down 0.065 0.065 0.065 n/a n/a a automatic power-down 209 286 329 n/a n/a a quiescent 9.83 12.34 13.58 n/a n/a ma low emi disabled software master power-down 0.065 0.065 0.065 2.68 7.542 a automatic power-down 0.065 0.065 0.065 43.72 7.542 a quiescent 2.51 4.62 5.6 0.945 6.182 ma enabled software master power-down 0.065 0.065 0.065 n/a n/a a automatic power-down 209 286 329 n/a n/a a quiescent 9.64 11.86 12.87 n/a n/a ma 1 n/a means not applicable. table 4. power supply current consumption, 8 + 33 h 1 edge rate control mode internal regulator i pvdd i dvdd i avdd test conditions pv dd = 5 v pv dd = 12 v pv dd = 16 v pv dd = 1.8 v pv dd = 5 v unit normal disabled software master power-down 0.065 0.065 0.065 2.68 7.542 a automatic power-down 0.065 0.065 0.065 43.72 7.542 a quiescent 2.59 5.02 6.31 0.942 6.432 ma enabled software master power-down 0.065 0.065 0.065 n/a n/a a automatic power-down 209 286 329 n/a n/a a quiescent 9.82 12.39 13.73 n/a n/a ma low emi disabled software master power-down 0.065 0.065 0.065 2.68 7.542 a automatic power-down 0.065 0.065 0.065 43.72 7.542 a quiescent 2.57 4.86 6.02 0.942 6.232 ma enabled software master power-down 0.065 0.065 0.065 n/a n/a a automatic power-down 209 286 329 n/a n/a a quiescent 9.65 12.02 13.18 n/a n/a ma 1 n/a means not applicable. table 5. power-down current parameter symbol test conditions/comments min typ max unit power-down current external avdd = 5 v and dvdd = 1.8 v, software master power-down, no bclk/fsync i pvdd pv dd = 5 v 65 na pv dd = 12 v 65 na pv dd = 16 v 65 na i avdd avdd = 5 v external 7.542 a i dvdd dvdd = 1.8 v external 2.7 a
SSM3582 data sheet rev. 0| page 8 of 59 digital input/output specifications table 6. parameter min typ max unit test conditions/comments input voltage 1 bclk, fsync, sdata, scl, and sda pins high (v ih ) 0.7 dv dd 5.5 v low (v il ) ?0.3 +0.3 dv dd v input leakage bclk, fsync, sdata, addrx, scl, and sda pins high (i ih ) 1 a low (i il ) 1 a input capacitance 5 pf output drive strength 1 sda 3 5 ma sample rate (fsync frequency) 8 192 khz 1 the pull-up resistor for scl and sda must be scaled according to the external pull-up voltage in the system. the typical value for a pull-up resistor for 1.8 v is 2.2 k. digital timing specifications all timing specifications are given for the default setting (i 2 s mode) of the serial input port. table 7. limit parameter min max unit description i 2 c port f scl 400 khz scl frequency t sclh 0.26 s scl high t scll 0.5 s scl low t scs 0.26 s setup time; relevant for repeated start condition t sch 0.26 s hold time; after this period, the first clock is generated t ds 50 ns data setup time t dh 0.14 s data hold time t scr 120 ns scl rise time t scf 120 ns scl fall time t sdr 120 ns sda rise time t sdf 120 ns sda fall time t bft 0.5 s bus free time (time between stop and start) digital input timing specifications table 8. limit parameter t min t max unit description serial port t bil 10 ns bclk low pulse width t bih 10 ns bclk high pulse width t sis 4 ns sdata setup; time to bclk rising t sih 4 ns sdata hold; time from bclk rising t lis 5 ns fsync setup time to bclk rising t lih 5 ns fsync hold time to bclk rising t bp 20 ns minimum bclk period
data sheet SSM3582 rev. 0| page 9 of 59 digital timing diagrams t sch t scs t bft t scf t ds t scll t scr t dh t sclh t sch stop condition start condition s d a scl t sdf t sdr 13399-002 figure 2. i 2 c port timing t sis t sih t sis t sih t lih t bp t bih bclk fsync sdata left-justified mode sdata i 2 c-justified mode sdata right-justified mode t bil t lis t sis t sih t sis t sih msb msb msb lsb msb ? 1 13399-003 figure 3. serial input port timing pvdd pvdd/2 t wu i 2 c power-up command output 0v 13399-104 figure 4. turn on time, hard volume
SSM3582 data sheet rev. 0| page 10 of 59 t sd i 2 c power-down command output pvdd 0v 13399-105 figure 5. turn off time, hard volume
data sheet SSM3582 rev. 0| page 11 of 59 absolute maximum ratings absolute maximum ratings apply at 25c, unless otherwise noted. table 9. parameter rating pvdd supply voltage ?0.3 v to +17 v dvdd supply voltage ?0.3 v to +1.98 v avdd supply voltage ?0.3 v to +5.5 v pgnd and agnd differential 0.3 v digital input pins fsync, bclk, sdata, scl, sda ?0.3 v to +5.5 v analog input pins addrx ?0.3 v to +1.98 v avdd_en ?0.3 v to +17 v dvdd_en ?0.3 v to +5.5 v esd susceptibility human body model 2 kv charged device model 1 kv storage temperature range ?65c to +150c operating temperature range ?40c to +85c junction temperature range ?65c to +150c lead temperature (soldering, 60 sec) 300c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja (junction to air) is specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. ja and jb are determined according to jesd51-9 on a 4-layer (2s2p) printed circuit board (pcb) with natural convection cooling. table 10. thermal resistance package type ja jc unit 40-lead, 6 mm 6 mm lfcsp 27 1.1 c/w esd caution
SSM3582 data sheet rev. 0| page 12 of 59 pin configuration and fu nction descriptions 1 pgnd 2 pgnd 3 avdd_en notes 1. use multiple vias to connect the exposed pad to the ground plane on the pcb. 4 scl 5 sda 6 fsync 7 sdata 8 bclk 9 pgnd 10 pgnd 23 dvdd_en 24 avdd 25 agnd 26 addr0 27 addr1 28 dvdd 29 pgnd 30 pgnd 22 pgnd 21 pgnd 1 1 b s t r + 1 2 o u t r + 1 3 o u t r + 1 5 p v d d 1 7 p v d d 1 6 p v d d 1 8 o u t r ? 1 9 o u t r ? 2 0 b s t r ? 1 4 p v d d 3 3 o u t l ? 3 4 p v d d 3 5 p v d d 3 6 p v d d 3 7 p v d d 3 8 o u t l + 3 9 o u t l + 4 0 b s t l + 3 2 o u t l ? 3 1 b s t l ? 13399-004 SSM3582 top view (not to scale) figure 6. pin configuration table 11. pin function descriptions pin no. mnemonic type 1 description 1 pgnd pwr left channel power stage ground. 2 pgnd pwr left channel power stage ground. 3 avdd_en ain 5 v avdd regulator enable. connect this pin to pvdd to enable the avdd regulator or connect to agnd to disable the regulator. when this pin is connected to pvdd, the regulator is enabled. when this pin is connected to agnd, the regulator is disabled. 4 scl din i 2 c clock input. 5 sda dio i 2 c data. 6 fsync din i 2 s/tdm frame sync (fsync) input. 7 sdata din i 2 s/tdm serial data (sdata) input. 8 bclk din i 2 s/tdm bit clock (bclk) input. 9 pgnd pwr right channel power stage ground. 10 pgnd pwr right channel power stage ground. 11 bstr+ ain bootstrap input, right channel noninverting. 12 outr+ aout right channel noninverting output. 13 outr+ aout right channel noninverting output. 14 pvdd pwr right channel power stage supply. 15 pvdd pwr right channel power stage supply. 16 pvdd pwr right channel power stage supply. 17 pvdd pwr right channel power stage supply. 18 outr? aout right channel inverting output. 19 outr? aout right channel inverting output. 20 bstr? ain bootstrap input, right channel inverting. 21 pgnd pwr right channel power stage ground. 22 pgnd pwr right channel power stage ground. 23 dvdd_en ain 1.8 v dvdd regulator enable. connect this pin to avdd to enable the dvdd regulator or connect to agnd to disable the regulator. when this pin is connected to avdd, the regulator is enabled. when this pin is connected to agnd, the regulator is disabled. 24 avdd pwr analog supply 5 v regulator output/external 5 v input. 25 agnd pwr analog ground. 26 addr0 ain address select 0 (see table 14). 27 addr1 ain address select 1 (see table 14). 28 dvdd pwr digital supply 1.8 v regulator output/external 1.8 v input. 29 pgnd pwr left channel power stage ground. 30 pgnd pwr left channel power stage ground. 31 bstl? ain bootstrap input, left channel inverting.
data sheet SSM3582 rev. 0| page 13 of 59 pin no. mnemonic type 1 description 32 outl? aout left channel inverting output. 33 outl? aout left channel inverting output. 34 pvdd pwr left channel power stage supply. 35 pvdd pwr left channel power stage supply. 36 pvdd pwr left channel power stage supply. 37 pvdd pwr left channel power stage supply. 38 outl+ aout left channel noninverting output. 39 outl+ aout left channel noninverting output. 40 bstl+ ain bootstrap input, left channel noninverting. epad exposed pad. use multiple vias to connect the exposed pad to the ground plane on the pcb. 1 pwr is power supply or ground pin, ain is analog input, din is digital input, dio is digital input/output, and aout is analog output.
SSM3582 data sheet rev. 0| page 14 of 59 typical performance characteristics 20 10 ?180 20 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k 13399-005 amplitude (dbv) frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 60dbfs input analog gain = 6.3v peak r l = 4 ? (low emi) figure 7. amplitude vs. frequency, 60 dbfs input, analog gain = 6.3 v peak 20 10 ?180 20 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k 13399-006 amplitude (dbv) frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 60dbfs input analog gain = 8.9v peak r l = 4 ? (low emi) figure 8. amplitude vs. frequency, 60 dbfs input, analog gain = 8.9 v peak 20 10 ?180 20 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k 13399-007 amplitude (dbv) frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 60dbfs input analog gain = 12.6v peak r l = 4 ? (low emi) figure 9. amplitude vs. frequency, 60 dbfs input, analog gain = 12.6 v peak 20 10 ?180 20 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k 13399-008 amplitude (dbv) frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 60dbfs input analog gain = 16v peak r l = 4 ? (low emi) figure 10. amplitude vs. frequency, 60 dbfs input, analog gain = 16 v peak 20 10 ?180 20 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k 13399-009 amplitude (dbv) frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 no signal analog gain = 6.3v peak r l = 4 ? (low emi) figure 11. amplitude vs. frequency, no signal, analog gain = 6.3 v peak 20 10 ?180 20 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k 13399-010 amplitude (dbv) frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 no signal analog gain = 8.9v peak r l = 4 ? (low emi) figure 12. amplitude vs. frequency, no signal, analog gain = 8.9 v peak
data sheet SSM3582 rev. 0| page 15 of 59 20 10 ?180 20 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k 13399-011 amplitude (dbv) frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 no signal analog gain = 12.6v peak r l = 4 ? (low emi) figure 13. amplitude vs. frequency, no signal, analog gain = 12.6 v peak 20 10 ?180 20 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k 13399-012 amplitude (dbv) frequency (hz) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 no signal analog gain = 16v peak r l = 4 ? (low emi) figure 14. amplitude vs. frequency, no signal, analog gain = 16 v peak 0.001 1.000 0.002 0.005 0.010 0.020 0.050 thd + n (%) 0.100 0.200 0.500 20 20k 50 100 200 500 frequency (hz) 13399-013 1k 2k 5k 10k 100mw 1w r l = 4 ? pv dd = 4.5v peak figure 15. thd + n vs. frequency, r l = 4 , pv dd = 4.5 v peak 0.001 1.000 0.002 0.005 0.010 0.020 0.050 thd + n (%) 0.100 0.200 0.500 20 20k 50 100 200 500 frequency (hz) 13399-014 1k 2k 5k 10k r l = 4 ? pv dd = 12v 5w 1w 100mw figure 16. thd + n vs. frequency, r l = 4 , pv dd = 12 v 0.001 1.000 0.002 0.005 0.010 0.020 0.050 thd + n (%) 0.100 0.200 0.500 20 20k 50 100 200 500 frequency (hz) 13399-015 1k 2k 5k 10k r l = 4 ? pv dd = 16v 10w 1w 100mw figure 17. thd + n vs. frequency, r l = 4 , pv dd = 16 v 0.001 1.000 0.002 0.005 0.010 0.020 0.050 thd + n (%) 0.100 0.200 0.500 20 20k 50 100 200 500 frequency (hz) 13399-016 1k 2k 5k 10k r l = 8 ? pv dd = 4.5v 100mw 500mw figure 18. thd + n vs. frequency, r l = 8 , pv dd = 4.5 v
SSM3582 data sheet rev. 0| page 16 of 59 0.001 1.000 0.002 0.005 0.010 0.020 0.050 thd + n (%) 0.100 0.200 0.500 20 20k 50 100 200 500 frequency (hz) 13399-017 1k 2k 5k 10k r l = 8 ? pv dd = 12v 5w 1w 100mw figure 19. thd + n vs. frequency, r l = 8 , pv dd = 12 v 0.001 1.000 0.002 0.005 0.010 0.020 0.050 thd + n (%) 0.100 0.200 0.500 20 20k 50 100 200 500 frequency (hz) 13399-018 1k 2k 5k 10k r l = 8 ? pv dd = 16v 5w 1w 100mw figure 20. thd + n vs. frequency, r l = 8 , pv dd = 16 v 0.001 10 0.002 0.005 0.010 0.020 0.050 0.100 0.200 thd + n (%) 0.500 1.000 2 5 10 50 20 50 100 200 500 1m 2m 5m 10m 20m power (w) 50m 100m 200m 500m 1 2 5 10 20 4.5v 7.0v 16.0v r l = 4 ? analog gain = 6.3v peak 13399-019 figure 21. thd + n vs. power, r l = 4 , analog gain = 6.3 v peak 0.001 10 0.002 0.005 0.010 0.020 0.050 0.100 0.200 thd + n (%) 0.500 1.000 2 5 50 1m 2m 5m 10m 20m power (w) 50m 100m 200m 500m 1 2 5 10 20 r l = 4 ? analog gain = 8.9v peak 13399-020 10 20 50 100 200 500 4.5v 12.0v 16.0v (3db gain added) figure 22. thd + n vs. power, r l = 4 , analog gain = 8.9 v peak 0.001 10 0.002 0.005 0.010 0.020 0.050 0.100 0.200 thd + n (%) 0.500 1.000 2 5 50 1m 2m 5m 10m 20m power (w) 50m 100m 200m 500m 1 2 5 10 20 4.5v 12.0v 16.0v r l = 4 ? analog gain = 12.6v peak 13399-021 10 20 50 100 200 500 figure 23. thd + n vs. power, r l = 4 , analog gain = 12.6 v peak 0.001 10 0.002 0.005 0.010 0.020 0.050 0.100 0.200 thd + n (%) 0.500 1.000 2 5 50 1m 2m 5m 10m 20m power (w) 50m 100m 200m 500m 1 2 5 10 20 4.5v 12.0v 16.0v r l = 4 ? analog gain = 16v peak 13399-022 10 20 50 100 200 500 figure 24. thd + n vs. power, r l = 4 , analog gain = 16 v peak
data sheet SSM3582 rev. 0| page 17 of 59 0.001 10 0.002 0.005 0.010 0.020 0.050 0.100 0.200 thd + n (%) 0.500 1.000 2 5 50 1m 2m 5m 10m 20m power (w) 50m 100m 200m 500m 1 2 5 10 20 4.5v 7.0v 16.0v r l = 8 ? analog gain = 6.3v peak 13399-023 10 20 50 100 200 500 figure 25. thd + n vs. power, r l = 8 , analog gain = 6.3 v peak 0.001 10 0.002 0.005 0.010 0.020 0.050 0.100 0.200 thd + n (%) 0.500 1.000 2 5 50 1m 2m 5m 10m 20m power (w) 50m 100m 200m 500m 1 2 5 10 20 4.5v 12.0v 16.0v r l = 8 ? analog gain = 8.9v peak 13399-024 10 20 50 100 200 500 figure 26. thd + n vs. power, r l = 8 , analog gain = 8.9 v peak 0.001 10 0.002 0.005 0.010 0.020 0.050 0.100 0.200 thd + n (%) 0.500 1.000 2 5 50 1m 2m 5m 10m 20m power (w) 50m 100m 200m 500m 1 2 5 10 20 4.5v 12.0v 16.0v r l = 8 ? analog gain = 12.6v peak 13399-025 10 20 50 100 200 500 figure 27. thd + n vs. power, r l = 8 , analog gain = 12. 6 v peak 0.001 10 0.002 0.005 0.010 0.020 0.050 0.100 0.200 thd + n (%) 0.500 1.000 2 5 10u 50 20u 50u 100u 200u 500u 1m 2m 5m 10m 20m power (w) 50m 100m 200m 500m 1 2 5 10 20 4.5v 12.0v 16.0v r l = 8 ? analog gain = 16v peak 13399-026 figure 28. thd + n vs. power, r l = 8 , analog gain = 16 v peak 0 1 2 3 4 5 6 7 56789101112 power (w) pv dd (v) 13399-028 analog gain = 6.3v peak r l = 4 ? p out = 10% p out = 1% figure 29. power vs. pv dd , r l = 4 , analog gain = 6.3 v peak 0 2 4 6 8 10 12 14 power (w) pv dd (v) p out = 10% p out = 1% 13399-027 analog gain = 8.9v peak r l = 4 ? 7891 01 11 2 figure 30. power vs. pv dd , r l = 4 , analog gain = 8.9 v peak
SSM3582 data sheet rev. 0| page 18 of 59 power (w) pv dd (v) 13399-029 0 5 10 15 20 25 30 7 9 11 13 15 p out = 10% p out = 1% analog gain = 12.6v peak r l = 4 ? figure 31. power vs. pv dd , r l = 4 , analog gain = 12.6 v peak power (w) pv dd (v) 13399-030 0 5 10 15 20 25 30 35 79111315 p out = 10% p out = 1% analog gain = 16v peak r l = 4 ? figure 32. power vs. pv dd , r l = 4 , analog gain = 16 v peak efficiency (%) p out (w) 13399-031 no ferrite bead, 220pf capacitor analog gain = 6.3v peak r l = 4 ? pv dd = 5v 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 normal emi low emi figure 33. efficiency vs. p out , no ferrite bead, analog gain = 6.3 v peak, r l = 4 , pv dd = 5 v efficiency (%) p out (w) 13399-032 no ferrite bead, 220pf capacitor analog gain = 8.9v peak r l = 4 ? pv dd = 7v 0 10 20 30 40 50 60 70 80 90 100 01234567 normal emi low emi figure 34. efficiency vs. p out , no ferrite bead, analog gain = 8.9 v peak, r l = 4 , pv dd = 7 v efficiency (%) p out (w) 13399-033 no ferrite bead, 220pf capacitor analog gain = 12.6v peak r l = 4 ? pv dd = 12v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 figure 35. efficiency vs. p out , no ferrite bead, analog gain = 12.6 v peak, r l = 4 , pv dd = 12 v efficiency (%) p out (w) 13399-034 no ferrite bead, 220pf capacitor analog gain = 16v peak r l = 4 ? pv dd = 16v 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 normal emi low emi figure 36. efficiency vs. p out , no ferrite bead, analog gain = 16 v peak, r l = 4 , pv dd = 16 v
data sheet SSM3582 rev. 0| page 19 of 59 p out (w) efficiency (%) p out (w) 13399-035 ferrite bead, 220pf capacitor analog gain = 6.3v peak r l = 4 ? pv dd = 5v 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 normal emi low emi figure 37. efficiency vs. p out , with ferrite bead, analog gain = 6.3 v peak, r l = 4 , pv dd = 5 v efficiency (%) p out (w) 13399-036 ferrite bead, 220pf capacitor analog gain = 8.9v peak r l = 4 ? pv dd = 7v 0 10 20 30 40 50 60 70 80 90 100 01234567 normal emi low emi figure 38. efficiency vs. p out , with ferrite bead, analog gain = 8.9 v peak, r l = 4 , pv dd = 7 v efficiency (%) p out (w) 13399-037 ferrite bead, 220pf capacitor analog gain = 12v peak r l = 4 ? pv dd = 12v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 0 5 10 15 20 figure 39. efficiency vs. p out , with ferrite bead, analog gain = 12 v peak, r l = 4 , pv dd = 12 v efficiency (%) p out (w) 13399-038 ferrite bead, 220pf capacitor analog gain = 16v peak r l = 4 ? pv dd = 16v 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 normal emi low emi figure 40. efficiency vs. p out , with ferrite bead, analog gain = 16 v peak, r l = 4 , pv dd = 16 v 0 0.002 0.004 0.006 0.008 0.010 57 9111315 p vdd (v) i pvdd (a) normal emi low emi 13399-039 no ferrite bead, 220pf capacitor analog gain = 12.6v peak r l = 4 ? figure 41. i pvdd vs. pv dd , no ferrite bead, analog gain = 12.6 v peak, r l = 4 0 0.002 0.004 0.006 0.008 0.010 57 9111315 p vdd (v) i pvdd (a) normal emi low emi 13399-040 no ferrite bead, 220pf capacitor analog gain = 12.6v peak r l = 4 ? figure 42. i pvdd vs. pv dd , no ferrite bead, analog gain = 12.6 v peak, r l = 4
SSM3582 data sheet rev. 0| page 20 of 59 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 56789101112 power (w) pv dd (v) 13399-041 analog gain = 6.3v peak r l = 8 ? p out = 10% p out = 1% figure 43. power vs. pv dd , analog gain = 6.3 v peak, r l = 8 0 1 2 3 4 5 6 7 7891 01 11 2 power (w) pv dd (v) 13399-042 analog gain = 8.9v peak r l = 8 ? p out = 10% p out = 1% figure 44. power vs. pv dd , analog gain = 8.9 v peak, r l = 8 0 2 4 6 8 10 12 14 7 8 9 10 11 12 13 14 15 16 pv dd (v) power (w) p out = 10% p out = 1% 13399-043 analog gain = 12.6v peak r l = 8 ? figure 45. power vs. pv dd , analog gain = 12.6 v peak, r l = 8 7 8 9 10 11 12 13 14 15 16 pv dd (v) power (w) p out = 10% p out = 1% 13399-044 0 2 4 6 8 10 12 14 16 18 20 analog gain = 16v peak r l = 8 ? figure 46. power vs. pv dd , analog gain = 16 v peak, r l = 8 efficiency (%) p out (w) 13399-045 no ferrite bead, 220pf capacitor analog gain = 6.3v peak r l = 8 ? pv dd = 5v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 00.51.01.52.0 figure 47. efficiency vs. p out , no ferrite bead, analog gain = 6.3 v peak, r l = 8 , pv dd = 5 v efficiency (%) p out (w) 13399-046 no ferrite bead, 220pf capacitor analog gain = 8.9v peak r l = 8 ? pv dd = 7v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 figure 48. efficiency vs. p out , no ferrite bead, analog gain = 8.9 v peak, r l = 8 , pv dd = 7 v
data sheet SSM3582 rev. 0| page 21 of 59 efficiency (%) p out (w) 13399-047 no ferrite bead, 220pf capacitor analog gain = 12.6v peak r l = 8 ? pv dd = 12v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 02468 12 10 figure 49. efficiency vs. p out , no ferrite bead, analog gain = 12.6 v peak, r l = 8 , pv dd = 12 v efficiency (%) p out (w) 13399-048 no ferrite bead, 220pf capacitor analog gain = 16v peak r l = 8 ? pv dd = 16v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 0 5 10 15 20 figure 50. efficiency vs. p out , no ferrite bead, analog gain = 16 v peak, r l = 8 , pv dd = 16 v efficiency (%) p out (w) 13399-049 ferrite bead, 220pf capacitor analog gain = 6.3v peak r l = 8 ? pv dd = 5v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 figure 51. efficiency vs. p out , with ferrite bead, analog gain = 6.3 v peak, r l = 8 , pv dd = 5 v efficiency (%) p out (w) 13399-050 ferrite bead, 220pf capacitor analog gain = 8.9v peak r l = 8 ? pv dd = 7v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 figure 52. efficiency vs. p out , with ferrite bead, analog gain = 8.9 v peak, r l = 8 , pv dd = 7 v efficiency (%) p out (w) 13399-051 ferrite bead, 220pf capacitor analog gain = 12.6v peak r l = 8 ? pv dd = 12v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 0 2.5 5.0 7.5 10.0 12.5 figure 53. efficiency vs. p out , with ferrite bead, analog gain = 12.6 v peak, r l = 8 , pv dd = 12 v efficiency (%) p out (w) 13399-052 ferrite bead, 220pf capacitor analog gain = 16v peak r l = 8 ? pv dd = 16v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 figure 54. efficiency vs. p out , with ferrite bead, analog gain = 16 v peak, r l = 8 , pv dd = 16 v
SSM3582 data sheet rev. 0| page 22 of 59 efficiency (%) p out (w) 13399-053 no ferrite bead, 220pf capacitor analog gain = 6.3v peak (mono) r l = 2 ? pv dd = 5v 0 10 20 30 40 50 60 70 80 90 100 01234567 normal emi low emi figure 55. efficiency vs. p out , no ferrite bead, analog gain = 6.3 v peak, r l = 2 , pv dd = 5 v efficiency (%) p out (w) 13399-054 no ferrite bead, 220pf capacitor analog gain = 8.9v peak (mono) r l = 2 ? pv dd = 7v 0 10 20 30 40 50 60 70 80 90 100 02468101214 normal emi low emi figure 56. efficiency vs. p out , no ferrite bead, analog gain = 8.9 v peak, r l = 2 , pv dd = 7 v efficiency (%) p out (w) 13399-055 no ferrite bead, 220pf capacitor analog gain = 12.6v peak (mono) r l = 2 ? pv dd = 12.6v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 0 5 10 15 20 25 30 35 40 figure 57. efficiency vs. p out , no ferrite bead, analog gain = 12.6 v peak, r l = 2 , pv dd = 12.6 v efficiency (%) p out (w) 13399-056 no ferrite bead, 220pf capacitor analog gain = 16v peak (mono) r l = 2 ? pv dd = 16v 0 10 20 30 40 50 60 70 80 90 100 0 10203040506070 normal emi low emi figure 58. efficiency vs. p out , no ferrite bead, analog gain = 16 v peak, r l = 2 , pv dd = 16 v efficiency (%) p out (w) 13399-057 no ferrite bead, 220pf capacitor analog gain = 6.3v peak (mono) r l = 3 ? pv dd = 5v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 figure 59. efficiency vs. p out , no ferrite bead, analog gain = 6.3 v peak, r l = 3 , pv dd = 5 v efficiency (%) p out (w) 13399-058 no ferrite bead, 220pf capacitor analog gain = 8.9v peak (mono) r l = 3 ? pv dd = 7v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 012345678910 figure 60. efficiency vs. p out , no ferrite bead, analog gain = 8.9 v peak, r l = 3 , pv dd = 7 v
data sheet SSM3582 rev. 0| page 23 of 59 efficiency (%) p out (w) 13399-059 no ferrite bead, 220pf capacitor analog gain = 12.6v peak (mono) r l = 3 ? pv dd = 12v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 0 5 10 15 20 25 30 figure 61. efficiency vs. p out , no ferrite bead, analog gain = 12.6 v peak, r l = 3 , pv dd = 12 v efficiency (%) p out (w) 13399-060 no ferrite bead, 220pf capacitor analog gain = 16v peak (mono) r l = 3 ? pv dd = 16v 0 10 20 30 40 50 60 70 80 90 100 normal emi low emi 0 5 10 15 20 25 30 35 40 45 50 figure 62. efficiency vs. p out , no ferrite bead, analog gain = 16 v peak, r l = 3 , pv dd = 16 v 0 2 4 6 8 10 12 14 56789101112 power (w) pv dd (v) 13399-061 p out = 10% p out = 1% analog gain = 8.9v peak (mono) r l = 4 ? figure 63. power vs. pv dd , analog gain = 8.9 v p-p, r l = 4 power (w) pv dd (v) 13399-062 0 5 10 15 20 25 30 7 8 9 101112 analog gain = 8.9v peak (mono) r l = 2 ? p out = 10% p out = 1% figure 64. power vs. pv dd , analog gain = 8.9 v peak, r l = 2 7 8 9 10 11 12 13 14 15 16 power (w) pv dd (v) 13399-063 0 10 20 30 40 50 60 p out = 10% p out = 1% analog gain = 12.6v peak (mono) r l = 2 ? figure 65. power vs. pv dd , analog gain = 12.6 v peak, r l = 2 7 8 9 10111213141516 pv dd (v) power (w) p out = 10% p out = 1% 13399-064 0 10 20 30 40 50 60 70 analog gain = 16v peak mono) r l = 2 ? figure 66. power vs. pv dd , analog gain = 16 v peak, r l = 2
SSM3582 data sheet rev. 0| page 24 of 59 56789101112 power (w) pv dd (v) 13399-065 p out = 10% p out = 1% 0 1 2 3 4 5 6 7 8 9 analog gain = 6.3v peak (mono) r l = 4 ? figure 67. power vs. pv dd , analog gain = 6.3 v peak, r l = 4 7891 01 11 2 power (w) pv dd (v) 13399-066 0 2 4 6 8 10 12 14 16 18 p out = 10% p out = 1% analog gain = 8.9v peak (mono) r l = 3 ? figure 68. power vs. pv dd , analog gain = 8.9 v peak r l = 3 7 8 9 10111213141516 pv dd (v) power (w) p out = 10% p out = 1% 13399-067 analog gain = 12.6v peak (mono) r l = 3 ? 0 5 10 15 20 25 30 35 figure 69. power vs. pv dd , analog gain = 12.6 v peak, r l = 3 7 8 9 10111213141516 pv dd (v) power (w) p out = 10% p out = 1% 13399-068 0 5 10 15 20 25 30 35 40 45 50 analog gain = 16v peak (mono) r l = 3 ? figure 70. power vs. pv dd , analog gain = 16 v peak, r l = 3
data sheet SSM3582 rev. 0| page 25 of 59 theory of operation overview the SSM3582 is a stereo, class-d audio amplifier with a filterless modulation scheme that greatly reduces external component count, conserving board space and reducing system cost. the SSM3582 does not require an output filter; it relies on the inherent induc- tance of the speaker coil and the natural filtering of the speaker and human ear to recover the audio component of the square wave output. most class-d amplifiers use some variation of pulse- width modulation (pwm) to generate the output switching pattern, whereas the SSM3582 uses - modulation, resulting in important benefits. - modulators do not produce a sharp peak with many harmonics in the am broadcast band, as pulse- width modulators often do. - modulation reduces the amplitude of spectral components at high frequencies, reducing emi emission that may otherwise radiate from speakers and long cable traces. due to the inherent spread spectrum nature of - modulation, the need for oscillator synchronization is eliminated for designs incorporating multiple SSM3582 amplifiers. the SSM3582 uses less power in quiescent conditions, which helps conserve the power drawn from the battery or power supply. the SSM3582 integrates overcurrent and temperature protection and a thermal warning with optional programmable automatic gain reduction. power supplies pvdd pvdd supplies the output power stages, as well as the low dropout (ldo) regulator for avdd and dvdd. avdd avdd is the analog supply used for the modulator, power stage driver, and other analog blocks. when the avdd_en pin = pvdd, the internal regulator generates 5 v and the avdd pin is used for decoupling only. when the avdd_en pin = agnd, 5 v must be provided to the avdd pin from an external system source, minimizing power losses. dvdd dvdd supplies the digital circuitry. the current in this node is very low, below 1 ma. when the dvdd_en pin = avdd, the internal regulator generates 1.8 v and the dvdd pin is used for decoupling only. when the dvdd_en pin = agnd, 1.8 v must be provided to the dvdd pin from an external system source, minimizing power losses. table 12 summarizes the power dissipation in various supply configurations, operating modes, and load characteristics. table 12. typical power supply current consumption for f s = 48 khz 1 avdd_ en pin load test conditions pvdd (v) 5 12 16 avdd pin i avdd (ma) i dvdd (ma) i pvdd (ma) total power (mw) i pvdd (ma) total power (mw) i pvdd (ma) total power (mw) low no load spwdn = 1 external 0.007542 0.00268 0.000065 0.042859 0.000065 0.043314 0.000065 0.043574 automatic power-down external 0.007542 0.04372 0.000065 0.116731 0.000065 0.117186 0.000065 0.117446 dither input external 6.335 0.945 2.54 46.076 4.94 92.656 6.25 133.376 pvdd no load spwdn = 1 internal n/a n/a 0.000065 0.000325 0.000065 0.00078 0.000065 0.00104 automatic power-down internal n/a n/a 0.209 1.045 0.286 3.432 0.329 5.264 dither input internal n/a n/a 9.78 48.9 12.38 148.56 14.05 224.8 low 8 + 33 h spwdn = 1 external 0.007542 0.00268 0.000065 0.042859 0.000065 0.043314 0.000065 0.043574 automatic power-down external 0.007542 0.04372 0.000065 0.116731 0.000065 0.117186 0.000065 0.117446 dither input external 6.432 0.942 2.59 46.8056 5.02 94.0956 6.31 134.8156 pvdd 8 + 33 h spwdn = 1 internal n/a n/a 0.000065 0.000325 0.000065 0.00078 0.000065 0.00104 automatic power-down internal n/a n/a 0.209 1.045 0.286 3.432 0.329 5.264 dither input internal n/a n/a 9.82 49.1 12.39 148.68 13.73 219.68 1 n/a means not applicable.
SSM3582 data sheet rev. 0| page 26 of 59 power-up sequence using only pvdd as a source when SSM3582 is used in single-supply mode, all internal rails are generated from pvdd. the internal avdd (5 v) and dvdd (1.8 v) regulators can be enabled by pulling the avdd_en and dvdd_en pins high. avdd_en is pulled to pvdd, and dvdd_en is pulled to avdd. the amplifier is operational and responds to i 2 c writes 10 ms after applying pvdd 5 v. using pvdd and external avdd take care when an external 5 v is supplied to avdd. the internal 5 v ldo must be disabled by pulling the avdd_en pin low. in this case, dvdd (1.8 v) is generated from pvdd. it is important to maintain pvdd > avdd to prevent the back powering of pvdd. using pvdd and external avdd and dvdd if using an external avdd and dvdd source, both the avdd_en and dvdd_en pins must be pulled low. it is important to maintain pvdd > avdd/dvdd to prevent back powering pvdd. dvdd must be present for the device to respond to i 2 c commands. the device becomes operational ~10 ms after dvdd is present. pvdd must be at least 5 v for the output stage to turn on, and must be 6 v for optimal performance. power-down operation the SSM3582 offers several power-down options via the i 2 c. register 0x04 provides multiple options for setting the various power-down modes. when set to 1, the spwdn bit fully powers down the device. in this case, only the i 2 c and 1.8 v regulator blocks, if enabled via the dvdd_en pin, are kept active. the SSM3582 monitors both the bclk and fsync pins for clock presence. when no bclk is present, the device automatically powers down all internal circuitry to its lowest power state. when bclk returns, the device automatically powers up following its usual power sequence. to guarantee click/pop free shutdown, power down the device via the spdwn control before clock removal. if enabled, the apwdn_en bit activates a low power state after 2048 consecutive zero input samples are received. only the i 2 c and digital audio input blocks are kept active. individual channels can be powered down using bits[3:2] in register 0x04. the temperature sense adc can be powered down using bit 5 in register 0x04. clocking a bclk signal must be provided to the SSM3582 for correct operation. the bclk signal must have a minimum frequency of 2.048 mhz. the bclk rate is autodetected, but the sampling frequency must be indicated. the bclk rates supported at 32 khz to 48 khz are 50, 64, 100, 128, 192, 200, 256, 384, 400, 512, 768, 800, and 1024 times the sample rate. digital audio serial interface the SSM3582 includes a standard serial audio interface that is slave only. the interface is capable of receiving i 2 s, left justified, pcm, or tdm formatted data. the serial interfaces have three main operating modes. the stereo modes, typically i 2 s or left justified, are used when there is a single chip on the interface bus. tdm mode is more flexible and offers the ability to have multiple chips on the bus. stereo operating modesi 2 s, left justified stereo modes use both edges of fsync to determine the placement of data. stereo mode is enabled when sai_mode = 0, and the i 2 s or left justified format is determined by the sdata_ fmt register setting. the i 2 s or left justified interface formats supports various bclk/fsync ratios (see table 13). sample rates from 8 khz to 192 khz are accepted. tdm operating mode the tdm operating mode allows multiple chips to connect to a single serial interface. the fsync signal operates at the desired sample rate. a rising edge of the fsync signal indicates the start of a new frame. for proper operation, this signal must be one bclk cycle wide, trans- itioning on a falling bclk edge. the msb of data is present on the sdata signal one bclk cycle later. the sdata signal is latched on a rising edge of bclk. each chip on the tdm bus can occupy 16, 24, 32, 48, or 64 bclk cycles, set via the tdm_bclks control bits. the maximum number of devices connected to a single tdm bus depends on the sample rate and number of bits per channel. the supported combinations of sample rates and bit depths are described in table 13. the maximum bit clock frequency is 49.152 mhz. using the tdm16 format, up to eight devices (16 channels) can be connected to a single tdm interface, and can operate at up to a 96k sample rate and at 32 bits per channel. see table 13 for the supported options at the 48 khz, 96 khz, and 192 khz sample rates. note that the interface is slave only, with the bit clock, frame sync, and data provided to the device. addrx pin settings dictate the default tdm slots for each device, and can be modified using the tdm_slot control register.
data sheet SSM3582 rev. 0| page 27 of 59 table 13. supported bclk rates in mhz 1 sample rate (khz) bclk/fsync ratio 50 64 100 128 192 200 256 384 512 768 800 1024 2048 4096 bclk (mhz) 2 8 to 12 n/a n/a n/a n/a n/a yes yes yes yes yes yes yes yes yes 16 to 24 n/a n/a yes yes yes yes yes yes yes yes yes yes yes n/a 32 to 48 yes yes yes yes yes yes yes yes yes yes yes yes n/a n/a 64 to 96 yes yes yes yes yes yes yes yes yes n/a n/a n/a n/a n/a 128 to 192 yes yes yes yes yes yes yes n/a n/a n/a n/a n/a n/a n/a 1 yes means that the specified rate is supported and n/a means not applicable. 2 bclk = (bclk/fsync ratio) sample rate. i 2 c control the SSM3582 supports an i 2 c-compatible, 2-wire serial bus, shared across multiple peripherals. two signals, serial data (sda) and serial clock (scl), carry information between the SSM3582 and the system i 2 c master controller. the SSM3582 is always a slave on the bus, and cannot initiate a data transfer. each slave device is identified by a unique address. the address byte format is shown in table 14. the address resides in the first seven bits of the i 2 c write. the lsb of this byte sets either a read or write operation. logic level 1 corresponds to a read operation, and logic level 0 corresponds to a write operation. for device address settings, see table 16. table 14. i 2 c device address byte format bit 7 bit 6 bit 5 bit 4 bit3 bit 2 bit 1 bit 0 0 0 1 bit 3 bit 2 addr0 addr1 r/w both sda and scl are open drain, and require pull-up resistors to the input/output voltage. the SSM3582 operates within the i 2 c voltage range of 1.6 v to 3.6 v. addressing initially, each device on the i 2 c bus is in an idle state, monitoring the sda and scl lines for a start condition and the proper address. the i 2 c master initiates a data transfer by establishing a start condition, defined by a high to low transition on sda while scl remains high. this start condition indicates that an address/ data stream follows. all devices on the bus respond to the start condition and shift the next eight bits (the 7-bit address plus the r/ w bit), msb first. the device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this ninth bit is known as an acknowledge bit. all other devices withdraw from the bus at this point and return to the idle condition. the device address for the SSM3582 is determined by the state of the addrx pins. see the device address setting section for more details. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the first byte means the master writes information to the peripheral, whereas a logic 1 means the master reads information from the peripheral after writing the subaddress and repeating the start address. a data transfer takes place until a stop condition is encountered. a stop condition occurs when sda transitions from low to high while scl is held high. the timing for the i 2 c port is shown in figure 71. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, the SSM3582 immediately jumps to the idle condition. during a given scl high period, issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid sub- address is issued, the SSM3582 does not issue an acknowledge and returns to the idle condition. if the user exceeds the highest sub- address while in automatic-increment mode, one of two actions is taken. in read mode, the SSM3582 outputs the highest subaddress register contents until the master device issues a no acknowledge, indicating the end of a read. a no acknowledge condition is a condition in which the sda line is not pulled low on the ninth clock pulse on scl. if the highest subaddress location is reached while in write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the SSM3582 , and the device returns to the idle condition. device address setting the device can be set at 16 different i 2 c addresses using the addr1 and addr0 pins, as well as 16 hardware modes. addr1 and addr0 are sampled during the start-up procedure. these pins set the appropriate operating mode, the i 2 c address, and the default tdm slots. the addrx pins can be set to five different voltage levels, as defined in table 15. the addrx pins are referenced to the dvdd rail of the device; connect pull-up resistors to the internally generated dvdd rail if the regulator is used. table 15. addrx pin input level mapping addrx state level (v) connected to ground 0 connected to ground using a 47 k resistor 0.45 left floating 0.9 connected to dvdd using a 47 k resistor 1.35 connected to dvdd 1.8
SSM3582 data sheet rev. 0| page 28 of 59 table 16. addrx pins to i 2 c device address and tdm slot mapping addrx pin state 1 device address default tdm slot addr0 addr1 mono = 0 mono = 1 0 0 0x10 1, 2 1 0 1 0x11 3, 4 2 1 0 0x12 5, 6 3 1 1 0x13 7, 8 4 0 pull-down 0x14 9, 10 5 0 pull-up 0x15 11, 12 6 1 pull-down 0x16 13, 15 7 1 pull-up 0x17 15, 16 8 pull-down 0 0x18 17, 18 9 pull-down 1 0x19 19, 20 10 pull-up 0 0x1a 21, 22 11 pull-up 1 0x1b 23, 24 12 pull-down pull-down 0x1c 25, 26 13 pull-down pull-up 0x1d 27, 28 14 pull-up pull-down 0x1e 29, 30 15 pull-up pull-up 0x1f 31, 32 16 1 0 = connect to ground, 1 = connect to dvdd. in the case of a pull-down state, connect to ground via a 47 k resistor. in the c ase of a pull-up stat e, connect to dvdd via a 47 k resistor. i 2 c read and write operations figure 72 shows the timing of a single-word write operation. every ninth clock, the SSM3582 issues an acknowledge by pulling sda low. figure 73 shows the timing of a burst mode write sequence. this figure shows an example where the target destination registers are two bytes. the SSM3582 knows to increment its subaddress register every byte because the requested subaddress corresponds to a register or memory area with a byte word length. the timing of a single-word read operation is shown in figure 74. note that the first r/ w bit is 0, indicating a write operation, because the subaddress must still be written to set up the internal address. after the SSM3582 acknowledges the receipt of the subaddress, the master must issue a repeated start command, followed by the chip address byte with the r/ w set to 1 (read). this repeated command causes the SSM3582 sda to reverse and to begin driving data back to the master. the master then responds every ninth pulse with an acknowledge pulse to the SSM3582 . refer to table 17 for a list of abbreviations in figure 72 through figure 75. table 17. abbreviations for figure 72 through figure 75 symbol meaning s start bit p stop bit a m acknowledge (ack used in figure 72 through figure 75) by master a s acknowledge (ack used in figure 72 through figure 75) by slave
data sheet SSM3582 rev. 0| page 29 of 59 r/w scl sda sda ( continued) scl ( continued) start by master frame1 chip address byte frame 2 subaddress byte frame 3 data byte 1 frame 4 data byte 2 stop by master ack ack ack ack 13399-069 figure 71. i 2 c read/write timing start bit stop bit r/w = 0 ack by slave ack by slave ic address (7 bits) subaddress (8 bits) data byte 1 (8 bits) 13399-070 figure 72. single-word i 2 c write format s chip address, r/w = 0 a s a s a s a s subaddress data- word 1 data- word 2 ?p 13399-071 figure 73. burst mode i 2 c write format s chip address, r/w = 0 chip address, r/w = 1 a s a s a s a m subaddress data byte 1 p data byte n s 13399-072 figure 74. single-word i 2 c read format s chip address, r/w = 0 chip address, r/w = 1 a s a s a s a m subaddress data- word 1 p ... s 13399-073 figure 75. burst mode i 2 c read format
SSM3582 data sheet rev. 0| page 30 of 59 standalone operation the SSM3582 can be operated in a standalone hardware control mode without any i 2 c control. the same addrx pins used to set the i 2 c device address are used to set the functionality of the device. in standalone mode, the i 2 c pins (scl and sda) are inputs and are shorted to dvdd or agnd to set the tdm slot/sample rate of the device (see table 18). in this case, the ana_gain bits are set to 11 and spwdn is set to 0 by default. in standalone mode, tdm slot selection, mono mode operation, and sample rate are selected via different pin settings. the device looks at the fsync signal and, if it is a 50% duty cycle, uses i 2 s settings. if the fysnc signal is a pulse, the device uses tdm settings. table 18. standalone mode pin settings and functionality sample rate pin states tdm slot(s) mono addr0 addr1 sda scl 32 khz to 48 khz 0 open 0 0 1, 2 0 1 open 0 0 3, 4 0 pull-down open 0 0 5, 6 0 pull-up open 0 0 7, 8 0 open 0 0 0 9, 10 0 open 1 0 0 11, 12 0 open pull-down 0 0 13, 14 0 open pull-up 0 0 15, 16 0 8 khz to 12 khz open open 0 0 1, 2 0 32 khz to 48 khz 0 open 0 1 1 1 1 open 0 1 2 1 pull-down open 0 1 3 1 pull-up open 0 1 4 1 open 0 0 1 5 1 open 1 0 1 6 1 open pull-down 0 1 7 1 open pull-up 0 1 8 1 8 khz to 12 khz open open 0 1 1, 2 1 64 khz to 96 khz 0 open 1 0 1, 2 0 1 open 1 0 3, 4 0 pull-down open 1 0 5, 6 0 pull-up open 1 0 7, 8 0 open 0 1 0 9, 10 0 open 1 1 0 11, 12 0 open pull-down 1 0 13, 14 0 open pull-up 1 0 15, 16 0 16 khz to 24 khz open open 1 0 1, 2 0 64 khz to 96 khz 0 open 1 1 1 1 1 open 1 1 2 1 pull-down open 1 1 3 1 pull-up open 1 1 4 1 open 0 1 1 5 1 open 1 1 1 6 1 open pull-down 1 1 7 1 open pull-up 1 1 8 1 128 khz to 192 khz open open 1 1 1, 2 0
data sheet SSM3582 rev. 0| page 31 of 59 mono mode the SSM3582 can be operated in mono mode for driving low impedance loads. in mono mode, the left and right power stages can be connected in parallel, as shown in figure 87. use caution when setting up mono mode. for proper operation, any hardware changes are required along with setting the register. for mono mode operation, set mono (register 0x04, bit 4) to 1. by default, this bit is set to 0 for stereo mode. after the bit is set for mono mode, only the left channel modulator is active and it feeds both the left and right channel power stages. the outl+ and outr+ pins are in phase. the outl? and outr? pins are also in phase. for mono mode, outl+ must be shorted to outr+; similarly, outl? must be shorted to outr?. in standalone mode, the addr0, addr1, scl, and sda pins determine the tdm slot. see the table 18 for the possible tdm slot configurations in mono mode. analog and digital gain four different gain settings are available to optimize the dynamic range of the amplifier in relation to the pvdd supply voltage. in software mode, the initial 19 db gain setting can be updated through the control interface. in standalone mode, the i 2 c interface pins set the gain of the device. table 19 summarizes the gain settings and load drive characteristics of the amplifier. the amplifier analog gain is set prior to enabling the device outputs and must not be changed during operation; a proper mute/unmute sequence is required to prevent audible transients between gain settings. finer level control is available in the digital domain, with a very flexible ?70 db to +24 db, 0.375 db/step ramp volume control and selectable nonaliasing clipping point. the digital volume control also includes a playback level limiter that can be set in tandem with the battery voltage monitor to prevent the amplifier from browning out the system when battery level is critically low. table 19. analog gain settings and drive characteristics ana_gain[1:0] gain, 1 v rms (db) v out 1 0 rms (v rms) peak-to-peak (v) 0 0 13 4.47 6.32 0 1 16 6.31 8.92 1 0 19 8.91 12.60 1 1 21 11.20 15.87 pop and click suppression pops and clicks are undesirable audible transients generated by the amplifier system that do not come from the system input signal. voltage transients as small as 10 mv can be heard as an audible pop in the speaker. voltage transients at the output of audio amplifiers often occur when shutdown is activated or deactivated. the SSM3582 has a pop and click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. set either mute or power-down before bclk is removed to ensure a pop free experience. temperature sensor the SSM3582 contains an 8-bit adc that measures the die temperature of the device and is enabled via the temp_pwdn bit in register 0x04. after the sensor is enabled, the temperature can be read via the i 2 c in the temp register, register 0x1b. the temperature information is stored in register 0x1b in an 8-bit, unsigned format. the adc input range is fixed internally from ?60c to +195c. to convert the hexadecimal value to the temperature (celsius) value, use the following steps: 1. convert the hexadecimal value to decimal and then subtract 60. for example, if the hexadecimal value is 0x54, the decimal value is 84. 2. calculate the temperature using the following equation: temperature = decimal value ? 60 with a decimal value of 84, temperature = 84 ? 60 = 24c
SSM3582 data sheet rev. 0| page 32 of 59 table 20. fault reporting registers fault type flag set condition status reported register pvdd undervoltage (uv) pvdd below <3.6 v register 0x18, bit 7, uvlo_pvdd 5 v regulator uv 5 v regulator voltage at avdd < 3.6 v register 0x18, bit 6, uvlo_vreg limiter/gain reduction engage left channel limi ter engaged register 0x19, bit 3, lim_eg_l right channel limiter engaged register 0x19, bit 7, lim_eg_r clipping, left channel left channel dac clipping register 0x19, bit 2, clip_l clipping, right channel right channel dac clipping register 0x19, bit 6, clip_r output overcurrent (oc) left channel output curren t > 6 a peak register 0x19, bit 1, amp_oc_l right channel output current > 6 a peak register 0x19, bit 5, amp_oc_r die overtemperature (ot) die temperature > 145c register 0x18, bit 1, otf die overtemperature warning (otw) die temperature > 117c register 0x18, bit 0, otw battery voltage > vbat_inf_x battery voltage pv dd > vbat_inf_l register 0x19, bit 0, bat_warn_l battery voltage pv dd > vbat_inf_r register 0x19, bit 4, bat_warn_r faults and limiter status reporting the SSM3582 offers comprehensive protections against the faults at the outputs and reporting to help with system design. the faults listed in table 20 are reported using the status registers. the faults listed in table 20 are reported in register 0x18 and register 0x19 and can be read via i 2 c by the microcontroller in the system. in the event of a fault occurrence, use register 0x0b to control how the device reacts to the faults. table 21. register 0x16, register 0x17, fault recovery fault type flag set condition status reported register otw the amount of gain reduction applied if there is an otw for left channel register 0x16, bits[1:0], otw_ gain_l the amount of gain reduction applied if there is an otw for the right channel register 0x16, bits[5:4], otw_ gain_r manual recovery use to attempt manual recovery in case of a fault event register 0x17, bit 7, mrcv autorecovery attempts when autorecovery from faults is used, set the number of attempts using this bit register 0x17, bits[5:4], max_ar uv recovery can be automatic or manual register 0x17, bit 2, arcv_uv die ot recovery can be automatic or manual register 0x17, bit 1, arcv_ot oc recovery can be automatic or manual register 0x17, bit 0, arcv_oc when the automatic recovery mode is set, the device attempts to recover itself after the fault event and, in case the fault persists, then the device sets the fault again. this process repeats until the fault is resolved. when the manual recovery mode is used, the device shuts down and the recovery must be attempted using the system micro- controller. vbat (pv dd ) sensing the SSM3582 contains an 8-bit adc that measures the voltage of the battery voltage (vbat/pv dd ) supply. the battery voltage information is stored in register 0x1a as an 8-bit unsigned format. the adc input range is fixed internally at 3.8 v to 16.2 v. to convert the hexadecimal value to the voltage value, use the following steps: convert the hexadecimal value to decimal. for example, if the hexadecimal value is 0xa9, the decimal value is 169. calculate the voltage using the following equation: voltage = 3.8 v + 12.4 v decimal value /255 with a decimal value of 169, voltage = 3.8 v + 12.4 v 169/255 = 12.02 v limiter and battery tracking threshold control the SSM3582 contains an output limiter that can be used to limit the peak output voltage of the amplifier. the limiter works on the rms and peak value of the signal. the limiter threshold, slope, attack rate, and release rate are programmable using register 0x0e, register 0x0f, and register 0x10 for the left channel and register 0x11, register 0x12, register 0x13 for the right channel. the limiter can be enabled or disabled using lim_en_l, bits[1:0] in register 0x0e, bits[1:0] for the left channel and the lim_en_r bits, bits[1:0] in register 0x11, for the right channel. the threshold at which the output is limited is determined by the lim_thres_l bits setting, bits[7:3] in register 0x0f for the left channel, and the lim_thres_r bits setting, bits[7:3] in register 0x12 for the right channel. when the ouput signal level exceeds the set threshold level, the limiter activates and limits the signal level to the set limit. below the set threshold, the output level is not affected.
data sheet SSM3582 rev. 0| page 33 of 59 the limiter threshold can be set above the maximum output voltage of the amplifier. in this case, the limiter allows maximum peak output; in other words, the output may clip depending on the power supply voltage and not the limiter. the limiter threshold can be set as fixed or to vary with the battery voltage via the vbat_track_l bit (register 0x0e, bit 2) for the left channel and vbat_track_r bit (register 0x11, bit 2) for right channel. when set to fixed, the limiter threshold is fixed and does not vary with battery voltage. the threshold can be set from 2 v peak to 16 v peak using the lim_thres_x bit (see figure 77). when set to a variable threshold, the SSM3582 monitors the vbat supply and automatically adjusts the limiter threshold based on the vbat supply voltage. the vbat supply voltage at which the limiter begins to decrease the output level is determined by the vbat inflection point (the vbat_inf _l bits (register 0x10, bits[7:0]) for the left channel and vbat_inf_r bits (register 0x13, bits[7:0]) for the right channel). the vbat_inf_x point is defined as the battery voltage at which the limiter either activates or deactivates depending on the lim_en_x mode (see table 22). when the battery voltage is greater than vbat_inf_x, the limiter is not active. when the battery voltage is less than vbat_inf_x, the limiter is activated. the vbat_inf_x bits can be set from 3.8 v to 16.2 v. the 8-bit value for the voltage can be calculated using the following equation: voltage = 3.8 + 12.4 decimal value /255 convert the decimal value to an 8-bit hexadecimal value and use it to set the vbat_inf_x bits. the slope bits (register 0x0f and register 0x12, bits[1:0]) determine the rate at which the limiter threshold is lowered relative to the amount of change in vbat below the vbat_inf_x point. the slope is the ratio of the limiter threshold reduction to the vbat voltage reduction. slope = limiter threshold / vbat the slope ratio can be set from 1:1 to 4:1. this function is useful to prevent early shutdown under low battery conditions. as the vbat voltage falls, the limiter threshold is lowered. this lower threshold results in the lower output level and therefore helps to reduce the current drawn from the battery and in turn helps prevent early shutdown due to low vbat. the limiter offers various active modes that can be set using the lim_en_x bits (register 0x0e and register 0x11, bits[1:0]) and the vbat_track_x bit, as shown in table 22. when lim_en_x = 01, the limiter is enabled. when lim_en_x = 10, the limiter mutes the output if vbat falls below vbat_inf_x. when lim_en_x = 11, the limiter engages only when the battery voltage is lower than vbat_inf_x. when vbat is greater than vbat_inf_x, no limiting occurs. note that there is hysteresis on vbat_inf_x for the limiter disengaging. the limiter, when active, reduces the gain of the amplifier. the rate of gain reduction or attack rate is determined by the lim_atr_ x bits (register 0x0e and register 0x11, bits[5:4]). similarly, when the signal level drops below the limiter threshold, the gain is restored. the gain release rate is determined by the lim_rrt bits (register 0x0e and register 0x11, bits[7:6]). input level peak output level amplifier clipping level lim_en_x = 00 vbat_track_x = 0 13399-076 figure 76. limiter example (lim_en_x = 0b0, vbat_track_x = 0bx) vbat lim_thres_x limiter threshold limiter threshold fixed at set value and does not track vbat 13399-077 figure 77. limiter fixed (lim_en_x = 0b01, vbat_track_x = 0b0) table 22. limiter modes lim_en_x vbat_track_x limiter vbat vbat_inf_x vbat vbat_inf_x comments 00 0 or 1 no not applicable not applicable see figure 76 01 0 fixed use the set threshold use the set threshold see figure 77 01 1 variable lowers the threshold use the set threshold see figure 78 and figure 79 10 0 or 1 fixed mutes the output use the set threshold not shown 11 0 fixed use the set threshold no limiting see figure 80 and figure 81 11 1 variable lowers the threshold no limiting see figure 82 and figure 83
SSM3582 data sheet rev. 0| page 34 of 59 input level limiter threshold setting peak output level vbat > vbat_inf_x limiter limiter threshold change for vbat < vbat_inf_x change in lim threshold = n (vbat_inf_x ? vbat) where n = 1 to 4, set using slope bits in reg 0x0f, reg 0x12 lim_en_x = 01 vbat_track_x = 1 13399-078 figure 78. limiter fixed (lim_en_x = 0b01, vbat_track_x = 0b1) vbat vbat_inf_x lim_thres_x slope limiter threshold lowers for vbat < vbat_inf_x limiter threshold stays at the set value for vbat > vbat_inf_x limiter threshold 13399-079 figure 79. output level vs. vbat in limiter tracking mode (lim_en_x = 0b01, vbat_track_x = 0b1) input level limiter threshold setting peak output level no change in lim threshold per vbat amplifier clipping level lim_en_x = 11 vbat_track_x = 0 13399-080 figure 80. limiter example (lim_en_x = 0b11, vbat_track_x = 0) vbat lim_thres_x limiter threshold limiter threshold fixed at set value and does not track vbat 13399-081 figure 81. limiter fixed (lim_en_x = 0b11, vbat_track_x = 0b0) input level limiter threshold setting peak output level vbat > vbat_inf_x limiter is not active limiter threshold change for vbat < vbat_inf change in lim threshold = n (vbat_inf_x ? vbat) where n = 1 to 4, set using slope bit in reg 0x0f, reg 0x12 amplifier clipping level lim_en_x = 11 vbat_track_x = 1 13399-082 figure 82. limiter example (lim_en_x = 0b11, vbat_track_x = 0b1) vbat vbat_inf_x set lim_thres_x slope limiter threshold lowers for vbat < vbat_inf_x limiter threshold inactive for vbat > vbat_inf_x limiter threshold 13399-083 figure 83. output level vs. vbat in limiter tracking mode (lim_en_x = 0b11, vbat_track_x = 0b1)
data sheet SSM3582 rev. 0| page 35 of 59 high frequency clipper the high frequency clipper can be controlled via the dac_clip_l bits (register 0x14, bits[7:0]) and the dacl_clip_r bits (register 0x15, bits[7:0]). these bits determine the clipper threshold, relative to full scale. when enabled, the clipper digitally clips the signal after the dac interpolation. emi noise the SSM3582 uses a proprietary modulation and spread spectrum technology to minimize emi emissions from the device. the SSM3582 passes fcc class-b emissions testing with an unshielded 20 inch ca ble using ferrite bead-based filtering. for applications that have difficulty passing fcc class-b emission tests, the SSM3582 includes an ultralow emi emissions mode that significantly reduces the radiated emissions at the class-d outputs, particularly above 100 mhz. note that reducing the supply voltage greatly reduces radiated emissions. output modulation description the SSM3582 uses three level, - output modulation. each output can swing from ground to pv dd , and vice versa. ideally, when no input signal is present, the output differential voltage is 0 v because there is no need to generate a pulse. in a real-world situation, noise sources are always present. due to this constant presence of noise, a differential pulse is occasionally generated in response to this stimulus. a small amount of current flows into the inductive load when the differential pulse is generated. however, typically, the output differential voltage is 0 v. this feature ensures that the current flowing through the inductive load is small. when the user sends an input signal, an output pulse is generated to follow the input voltage. the differential pulse density is increased by raising the input signal level. figure 84 depicts three-level, - output modulation with and without input stimulus. output > 0v +5v 0v o utx+ +5v 0v outx? +5v 0v v out output < 0v +5v 0v o utx+ +5v 0v outx? 0v ?5v v out output = 0v o utx+ +5v 0v +5v 0v outx? +5v ?5v 0v v out 13399-074 figure 84. three-level, - output modu lation with and without input stimulus
SSM3582 data sheet rev. 0| page 36 of 59 bootstrap capacitors the output stage of the SSM3582 uses a high-side nmos driver, rather than a pmos driver. to generate the gate drive voltage for the high-side nmos, a bootstrap capacitor for each output terminal acts as a floating power supply for the switching cycle. use 0.22 f capacitors to connect the appropriate output pin (outx) to the bootstrap pin (bstx). for example, connect a 0.22 f capacitor between outl+ (a left channel, noninverting output) and bstl+ for bootstrapping the left channel. similarly, connect another 0.22 f capacitor between the outl? and bstl? pins for the left channel inverting output. power supply decoupling to ensure high efficiency, low thd, and high psrr, proper power supply decoupling is necessary. noise transients on the power supply lines are short duration voltage spikes. these spikes can contain frequency components that extend into the hundreds of megahertz. the power supply input must be decoupled with a good quality, low esl, low esr bulk capacitor larger than 220 f. this capacitor bypasses low frequency noise to the ground plane. for high frequency decoupling, place 1 f capacitors as close as possible to the pvdd pins of the device. output emi filtering additional emi filtering may be required when the speaker traces and cables are long and present a significant capacitive load that can create additional draw from the amplifier. typical power ferrites present a significant magnetic hysteresis cycle that affects thd performance and are not recommended for high performance designs. the nfz filter series from murata, designed in close collaboration with analog devices, inc., provides a closed hysteresis loop similar to an air coil with minimum impact on performance. products are available at upwards of 4 a rms, well suited to this application. a small capacitor can be added between the output of the filter and ground to further attenuate very high frequencies. take care to ensure the capacitor is properly sized so as not to affect idle power consumption or efficiency. pcb placement component selection and placement have great influence on system performance, both measured and subjective. proper pvdd layout and decoupling is necessary to reach the specified level of performance, particularly at the highest power levels. the placement shown in figure 85 ensures proper output stage decoupling for each channel, for minimum supply noise and maximum separation between channels. additional bulk decoupling is necessary to reduce current ripple at low frequencies, and can be shared between several amplifiers in a multichannel solution. 13399-075 bstl+ 0.22f capacitor pvdd decoupling 0.1f capacitor bstl? 0.22f capacitor dvdd decoupling 0.1f capacitor avdd decoupling 0.1f capacitor bstr+ 0.22f capacitor bstr? 0.22f capacitor pvdd decoupling 0.1f capacitor figure 85. recommended component placement
data sheet SSM3582 rev. 0| page 37 of 59 layout as output power increases, care must be taken to lay out pcb traces and wires properly among the amplifier, load, and power supply; a poor layout increases voltage drops, consequently decreasing efficiency. a good practice is to use short, wide pcb tracks to decrease voltage drops and minimize inductance. for the lowest dc resistance (dcr) and minimum inductance, ensure that track widths for the outputs are at least 200 mil for every inch of length and use 1 oz. or 2 oz. copper. to maintain high output swing and high peak output power, the pcb traces that connect the output pins to the load and supply pins must be as wide as possible; this also maintains the minimum trace resistances. in addition, good pcb layout isolates critical analog paths from sources of high interference. separate high frequency circuits (analog and digital) from low frequency circuits. pvdd and pgnd carry most of the device current, and must be properly decoupled with multiple capacitors at the device pins. to minimize ground bounce, use independent large traces to carry pvdd and pgnd to the power supply, thus reducing the amount of noise the amplifier bridges inject in the circuit, particularly if common ground impedance is significant. proper grounding guidelines help improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. properly designed multilayer pcbs can reduce emi emission and increase immunity to the rf field by a factor of 10 or more, compared with double-sided boards. a multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. if the system has separate analog and digital ground and power planes, the analog ground plane must be directly beneath the analog power plane, and, similarly, the digital ground plane must be directly beneath the digital power plane. there must be no overlap between the analog and digital ground planes or between the analog and digital power planes.
SSM3582 data sheet rev. 0| page 38 of 59 register summary table 23. register summary reg name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 vendor_id [7:0] vendor 0x41 r 0x01 device_id1 [7:0] device1 0x35 r 0x02 device_id2 [7:0] device2 0x82 r 0x03 revision [7:0] rev 0x01 r 0x04 power_ctrl [7:0] apwdn_en reserved temp_pwd n mono r_pwdn l_pwdn reserved spwdn 0xa1 r/w 0x05 amp_dac_ctrl [7:0] dac_lpm reserved dac_pol_r dac_pol_l edge reserved ana_gain 0x8a r/w 0x06 dac_ctrl [7:0] dac_hv dac_mute_r dac_ mute_l dac_hpf reserved dac_fs 0x02 r/w 0x07 vol_left_ctrl [7:0] vol_l 0x40 r/w 0x08 vol_right_ctrl [7:0] vol_r 0x40 r/w 0x09 sai_ctrl1 [7:0] reserved bclk_pol tdm_bclks fsync_mode sdata_fmt sai_mode 0x11 r/w 0x0a sai_ctrl2 [7:0] sdata_edge reserved data_width vol_zc_only clip_link vol_link auto_slot 0x07 r/w 0x0b slot_left_ctrl [7:0] reserved tdm_slot_l 0x00 r/w 0x0c slot_right_ctrl [7:0] reserved tdm_slot_r 0x01 r/w 0x0e lim_left_ctrl1 [7:0] lim_rrt_l lim_atr_l reserved vbat_track_l lim_en_l 0xa0 r/w 0x0f lim_left_ctrl2 [7:0] lim_thres_l reserved slope_l 0x51 r/w 0x10 lim_left_ctrl3 [7:0] vbat_inf_l 0x22 r/w 0x11 lim_right_ctrl1 [7:0] lim_rrt_r lim_atr_r lim_link vbat_track_r lim_en_r 0xa8 r/w 0x12 lim_right_ctrl2 [7:0] lim_th res_r reserved slope_r 0x51 r/w 0x13 lim_right_ctrl3 [7:0] vbat_inf_r 0x22 r/w 0x14 clip_left_ctrl [7:0] dac_clip_l 0xff r/w 0x15 clip_right_ctrl [7:0] dac_clip_r 0xff r/w 0x16 fault_ctrl1 [7:0] reserved otw_ga in_r reserved otw_gain_l 0x00 r/w 0x17 fault_ctrl2 [7:0] mrcv reserved max_ar reserved arcv_uv arcv_ot arcv_oc 0x30 r/w 0x18 status1 [7:0] uvlo_pvdd uvlo_vreg reserved otf otw 0x00 r 0x19 status2 [7:0] lim_eg_r clip_r amp_oc_r bat_wa rn_r lim_eg_l clip_l amp_oc_l bat_warn_l 0x00 r 0x1a vbat [7:0] vbat 0x00 r 0x1b temp [7:0] temp 0x00 r 0x1c soft_reset [7:0] reserved s_rst 0x00 r/w
data sheet SSM3582 rev. 0| page 39 of 59 register details address: 0x00, reset: 0x41, name: vendor_id table 24. bit descriptions for vendor_id bits bit name settings description reset access [7:0] vendor vendor id 0x41 r address: 0x01, reset: 0x35, name: device_id1 table 25. bit descriptions for device_id1 bits bit name settings description reset access [7:0] device1 device id 1 0x35 r address: 0x02, reset: 0x82, name: device_id2 table 26. bit descriptions for device_id2 bits bit name settings description reset access [7:0] device2 device id 2 0x82 r address: 0x03, reset: 0x01, name: revision table 27. bit descriptions for revision bits bit name settings description reset access [7:0] rev revision code 0x1 r 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 [7:0] rev (r) revision code 7 1 6 0 5 0 4 0 3 0 2 0 1 1 0 0 [7:0] device2 (r) device id 2 7 0 6 0 5 1 4 1 3 0 2 1 1 0 0 1 [7:0] device1 (r) device id 1 7 0 6 1 5 0 4 0 3 0 2 0 1 0 0 1 [7:0] vendor (r) vendor id
SSM3582 data sheet rev. 0| page 40 of 59 address: 0x04, reset: 0xa1, name: power_ctrl a uto power-down enable 1: auto power-down feature enabled. 0: auto power-down feature disabled. software master power-down 1: software master power-down. 0: normal operation. temperature sensor power-down 1: temperature sensor powered down. 0: temperature sensor on. left channel power-down 1: left channel powered down. 0: left channel powered on. mo n o mo d e se le cti o n 1: stereo mode enabled. 0: mono mode enabled. right channel power-down 1: right channel powered down. 0: right channel powered on. 0 1 1 0 2 0 3 0 4 0 5 1 6 0 7 1 [7] apw dn_en (r/w ) [0] spw dn (r/w ) [6] reserved [1] reserved [5] temp_pwdn (r/w) [2] l_pwdn (r/w) [4] mono (r/w) [3] r_pwdn (r/w) table 28. bit descriptions for power_ctrl bits bit name settings description reset access 7 apwdn_en automatic power-down enable. 0x1 r/w 0 automatic power-down feature disabled. 1 automatic power-down feature enabled. 6 reserved reserved. 0x0 r 5 temp_pwdn temperature sensor power-down. 0x1 r/w 0 temperature sensor on. 1 temperature sensor powered down. 4 mono mono mode selection. 0x0 r/w 0 mono mode enabled. 1 stereo mode enabled. 3 r_pwdn left channel power-down. 0x0 r/w 0 right channel powered on. 1 right channel powered down. 2 l_pwdn left channel power-down. 0x0 r/w 0 left channel powered on. 1 left channel powered down. 1 reserved reserved. 0x0 r 0 spwdn software master power-down 0x1 r/w 0 normal operation. 1 software master power-down.
data sheet SSM3582 rev. 0| page 41 of 59 address: 0x05, reset: 0x8a, name: amp_dac_ctrl dac low power mode 1: dac low power mode enabled. 0: dac low power mode disabled. amplifier analog gain select 11: +21 db (16 v peak) 10: +19 db (12.6 v peak) 1: +16 db (8.9 v peak) 0: +13db (6.3 v peak) right channel dac output polarity control 1: invert the dac output. 0: normal behavior. edge rate control 1: low emi mode operation. 0: normal operation. left channel dac output polarity control 1: invert the dac output. 0: normal behavior. 0 0 1 1 2 0 3 1 4 0 5 0 6 0 7 1 [7] dac_lpm (r/w) [1:0] ana_gain (r/w) [6] reserved [2] reserved [5] dac_pol_r (r/w) [3] edge (r/w) [4] dac_pol_l (r/w) table 29. bit descriptions for amp_dac_ctrl bits bit name settings description reset access 7 dac_lpm dac low power mode. 0x1 r/w 0 dac low power mode disabled. 1 dac low power mode enabled. 6 reserved reserved. 0x0 r 5 dac_pol_r right channel dac o utput polarity control. 0x0 r/w 0 normal behavior. 1 invert the dac output. 4 dac_pol_l left channel dac output polarity control. 0x0 r/w 0 normal behavior. 1 invert the dac output. 3 edge edge rate control. 0x1 r/w 0 normal operation. 1 low emi mode operation. 2 reserved reserved. 0x0 r [1:0] ana_gain amplifier analog gain select. 0x2 r/w 0 +13 db (6.3 v peak). 1 +16 db (8.9 v peak). 10 +19 db (12.6 v peak). 11 +21 db (16 v peak).
SSM3582 data sheet rev. 0| page 42 of 59 address: 0x06, reset: 0x02, name: dac_ctrl hard volume control 1: no volume ramping. 0: soft volume ramping. dac sample rate select 101: 48khz to 72 khz. 100: 128khz to 192 khz. 11: 64khz to 96 khz. 10: 32khz to 48 khz. 1: 16khz to 24 khz. 0: 8khz to 12 khz. dac right channel mute 1: right channel muted. 0: right channel unmuted. dac left channel mute 1: left channel muted. 0: left channel unmuted. dac high pass filter 1: dac high pass filter enabled. 0: dac high pass filter disabled. 0 0 1 1 2 0 3 0 4 0 5 0 6 0 7 0 [7] dac_hv (r/w ) [2:0] dac_fs (r/w ) [6] dac_mute_r (r/w ) [3] reserved [5] dac_mute_l (r/w ) [4] dac_hpf (r/w ) table 30. bit descriptions for dac_ctrl bits bit name settings description reset access 7 dac_hv hard volume control. 0x0 r/w 0 soft volume ramping. 1 no volume ramping. 6 dac_mute_r dac right channel mute. 0x0 r/w 0 right channel unmuted. 1 right channel muted. 5 dac_mute_l dac left channel mute. 0x0 r/w 0 left channel unmuted. 1 left channel muted. 4 dac_hpf dac high-pass filter. 0x0 r/w 0 dac high-pass filter disabled. 1 dac high-pass filter enabled. 3 reserved reserved. 0x0 r [2:0] dac_fs dac sample rate select. 0x2 r/w 0 8 khz to 12 khz. 1 16 khz to 24 khz. 10 32 khz to 48 khz. 11 64 khz to 96 khz. 100 128 khz to 192 khz. 101 48 khz to 72 khz.
data sheet SSM3582 rev. 0| page 43 of 59 address: 0x07, reset: 0x40, name: vol_left_ctrl left channel volume 0xff: mute. 0xfe: -71.25 db. 0xfd: -70.875 db. ... 0x02: ... 0x01: +23.625 db. 0x00: +24 db. 0 0 1 0 2 0 3 0 4 0 5 0 6 1 7 0 [7:0] vol_l (r/w) table 31. bit descriptions for vol_left_ctrl bits bit name settings description reset access [7:0] vol_l left channel volume 0x40 r/w 0x00 +24 db 0x01 +23.625 db 0x02 0x3f +0.375 db 0x40 0 db 0x41 ?0.375 db 0x42 0xfd ?70.875 db 0xfe ?71.25 db 0xff mute address: 0x08, reset: 0x40, name: vol_right_ctrl right channel volume 0xff: mute. 0xfe: -71.25 db. 0xfd: -70.875 db. ... 0x02: ... 0x01: +23.625 db. 0x00: +24 db. 0 0 1 0 2 0 3 0 4 0 5 0 6 1 7 0 [7:0] vol_r (r/w) table 32. bit descriptions for vol_right_ctrl bits bit name settings description reset access [7:0] vol_r right channel volume 0x40 r/w 0x00 +24 db 0x01 +23.625 db 0x02 0x3f +0.375 db 0x40 0 db 0x41 ?0.375 db 0x42 0xfd ?70.875 db 0xfe ?71.25 db 0xff mute
SSM3582 data sheet rev. 0| page 44 of 59 address: 0x09, reset: 0x11, name: sai_ctrl1 serial interface mode select 1: tdm modes. 0: stereo modes. bclk polarity control 1: use falling edge to capture sdata. 0: use rising edge to capture sdata. serial data form at 1: left justified format. 0: i2s (delay by 1) format. tdm slot width select 100: 64 bits. 11: 48 bits. 10: 32 bits. 1: 24 bits. 0: 16 bits. fsync m ode 1: tdm: frame start on rising edge. stereo: high fsync is left channel; 0: tdm: frame start on falling edge. stereo: low fsync is left channel; 0 1 1 0 2 0 3 0 4 1 5 0 6 0 7 0 [7] reserved [0] sai_mode (r/w) [6] bclk_pol (r/w) [1] sdata_fmt (r/w) [5:3] tdm_bclks (r/w) [2] fsync_mode (r/w) table 33. bit descriptions for sai_ctrl1 bits bit name settings description reset access 7 reserved reserved. 0x0 r 6 bclk_pol bclk polarity control 0x0 r/w 0 use rising edge to capture sdata 1 use falling edge to capture sdata [5:3] tdm_bclks tdm slot width select 0x2 r/w 0 16 bits 1 24 bits 10 32 bits 11 48 bits 100 64 bits 2 fsync_mode fsync mode 0x0 r/w 0 stereo: low fsync is left channel; tdm: frame start on falling edge 1 stereo: high fsync is left channel; tdm: frame start on rising edge 1 sdata_fmt serial data format 0x0 r/w 0 i 2 s (delay by 1) format 1 left justified format 0 sai_mode serial interface mode select 0x1 r/w 0 stereo modes 1 tdm modes
data sheet SSM3582 rev. 0| page 45 of 59 address: 0x0a, reset: 0x07, name: sai_ctrl2 sdata edge delay mode 1: half cycle delay of sdata. 0: normal operation. autom atic tdm s lot s election 1: addrx pin settings. set tdm s lots autom atically us ing 0: bits. set tdm slots using tdm_slotx channel volume link 1: link both channels to vol_l control. 0: controls. use independent vol_l and vol_r a udio input data width 1: 16 bits. 0: 24 bits. high frequency clipper link 1: bits. link both channels to dac_clip_l 0: bits. use independent left and right dac_clip_ x volume control zero-crossing detection 1: is detected (may be different per-channel) only change volume when zero-crossing 0: allow volume to change at all times. 0 1 1 1 2 1 3 0 4 0 5 0 6 0 7 0 [7] sdata_edge (r/w) [0] auto_slot (r/w) [6:5] reserved [1] vol_link (r/w) [4] data_width (r/w) [2] clip_link (r/w) [3] vol_zc_only (r/w) table 34. bit descriptions for sai_ctrl2 bits bit name settings description reset access 7 sdata_edge sdata edge delay mode 0x0 r/w 0 normal operation 1 half cycle delay of sdata [6:5] reserved reserved 0x0 r 4 data_width audio input data width 0x0 r/w 0 24 bits 1 16 bits 3 vol_zc_only volume control zero-crossing detection 0x0 r/w 0 allow volume to change at all times 1 only change volume when zero-crossing is detected (may be different per channel) 2 clip_link high frequency clipper link 0x1 r/w 0 use independent left and right dac_clip_x bits 1 link both channels to dac_clip_l bits 1 vol_link channel volume link 0x1 r/w 0 use independent vol_l and vol_r controls 1 link both channels to vol_l control 0 auto_slot automatic tdm slot selection 0x1 r/w 0 set tdm slots using tdm_slot_x bits 1 set tdm slots automatically using the addrx pin settings
SSM3582 data sheet rev. 0| page 46 of 59 address: 0x0b, reset: 0x00, name: slot_left_ctrl left channel slot selection 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [4:0] tdm_slot_l (r/w) table 35. bit descriptions for slot_left_ctrl bits bit name settings description reset access [7:5] reserved reserved 0x0 r [4:0] tdm_slot_l left channel slot selection 0x0 r/w address: 0x0c, reset: 0x01, name: slot_right_ctrl right channel slot selection 0 1 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:5] reserved [4:0] tdm_slot_r (r/w) table 36. bit descriptions for slot_right_ctrl bits bit name settings description reset access [7:5] reserved reserved 0x0 r [4:0] tdm_slot_r right channel slot selection 0x1 r/w address: 0x0e, reset: 0xa0, name: lim_left_ctrl1 left limiter release rate 11: 800 ms/db. 10: 1200 ms/db. 1: 1600 ms/db. 0: 3200 ms/db. left limiter mode 11: limiter on only if vbat data sheet SSM3582 rev. 0| page 47 of 59 bits bit name settings description reset access 2 vbat_track_l left thresh old battery tracking 0x0 r/w 0 fixed limiter threshold set by lim_thres bits in register 0x0f 1 ramp down limiter threshold when vb at < vbat_inf_l using slope_x bits in register 0x0f. [1:0] lim_en_l left limiter mode 0x0 r/w 0 limiter off 1 limiter on 10 mute output if vbat < vbat_inf_l. 11 limiter on only if vbat < vbat_inf_l. address: 0x0f, reset: 0x51, name: lim_left_ctrl2 left lim iter thres hold 31: 2 v peak. 30: 2.5 v peak. 29: 3 v peak. ... 2: 15 v peak. 1: 15.5 v peak. 0: 16 v peak. left limiter threshold reduction slope 11: 4:1 threshold:vbat reduction . 10: 3:1 threshold:vbat reduction . 1: 2:1 threshold:vbat reduction . 0: 1:1 threshold:vbat reduction . 0 1 1 0 2 0 3 0 4 1 5 0 6 1 7 0 [7:3] lim_thres_l (r/w) [1:0] slope_l (r/w) [2] reserved table 38. bit descriptions for lim_left_ctrl2 bits bit name settings description reset access [7:3] lim_thres_l left limiter threshold 0xa r/w 0 16 v peak 1 15.5 v peak 2 15 v peak 3 14.5 v peak 4 14 v peak 5 13.5 v peak 6 13 v peak 7 12.5 v peak 8 12 v peak 9 11.5 v peak 10 11 v peak 11 10.5 v peak 12 10 v peak 13 9.5 v peak 14 9.25 v peak 15 9 v peak 16 8.75 v peak 17 8.5 v peak 18 8.25 v peak 19 8 v peak 20 7.5 v peak
SSM3582 data sheet rev. 0| page 48 of 59 bits bit name settings description reset access 21 7 v peak 22 6.5 v peak 23 6 v peak 24 5.5 v peak 25 5 v peak 26 4.5 v peak 27 4 v peak 28 3.5 v peak 29 3 v peak 30 2.5 v peak 31 2 v peak 2 reserved reserved 0x0 r [1:0] slope_l left limiter threshold reduction slope 0x1 r/w 0 1:1 threshold: vbat reduction 1 2:1 threshold: vbat reduction 10 3:1 threshold: vbat reduction 11 4:1 threshold: vbat reduction address: 0x10, reset: 0x22, name: lim_left_ctrl3 left limiter battery voltage inflection point 0 0 1 1 2 0 3 0 4 0 5 1 6 0 7 0 [7:0] vbat_inf_l (r/w) table 39. bit descriptions for lim_left_ctrl3 bits bit name settings description reset access [7:0] vbat_inf_l left limiter batt ery voltage inflection point 0x22 r/w
data sheet SSM3582 rev. 0| page 49 of 59 address: 0x11, reset: 0xa8, name: lim_right_ctrl1 right limiter release rate 11: 800 ms/db. 10: 1200 ms/db. 1: 1600 ms/db. 0: 3200 ms/db. right limiter mode 11: lim iter on only if vbat SSM3582 data sheet rev. 0| page 50 of 59 address: 0x12, reset: 0x51, name: lim_right_ctrl2 right limiter threshold 31: 2 vp. 30: 2.5 vp. 29: 3 vp. ... 2: 15 vp. 1: 15.5 vp. 0: 16 vp. right limiter threshold reduction slope 11: 4:1 threshold:vbat reduction. 10: 3:1 threshold:vbat reduction. 1: 2:1 threshold:vbat reduction. 0: 1:1 threshold:vbat reduction. 0 1 1 0 2 0 3 0 4 1 5 0 6 1 7 0 [7:3] lim_thres_r (r/w) [1:0] slope_r (r/w) [2] reserved table 41. bit descriptions for lim_right_ctrl2 bits bit name settings description reset access [7:3] lim_thres_r right limiter threshold 0xa r/w 0 16 v p-p 1 15.5 v p-p 2 15 v p-p 3 14.5 v p-p 4 14 v p-p 5 13.5 v p-p 6 13 v p-p 7 12.5 v p-p 8 12 v p-p 9 11.5 v p-p 10 11 v p-p 11 10.5 v p-p 12 10 v p-p 13 9.5 v p-p 14 9.25 v p-p 15 9 v p-p 16 8.75 v p-p 17 8.5 v p-p 18 8.25 v p-p 19 8 v p-p 20 7.5 v p-p 21 7 v p-p 22 6.5 v p-p 23 6 v p-p 24 5.5 v p-p 25 5 v p-p 26 4.5 v p-p 27 4 v p-p 28 3.5 v p-p 29 3 v p-p 30 2.5 v p-p 31 2 v p-p
data sheet SSM3582 rev. 0| page 51 of 59 bits bit name settings description reset access 2 reserved reserved 0x0 r [1:0] slope_r right limiter threshold reduction slope 0x1 r/w 0 1:1 threshold: vbat reduction 1 2:1 threshold: vbat reduction 10 3:1 threshold: vbat reduction 11 4:1 threshold: vbat reduction address: 0x13, reset: 0x22, name: lim_right_ctrl3 right limiter battery voltage inflection point 0 0 1 1 2 0 3 0 4 0 5 1 6 0 7 0 [7:0] vbat_inf_r (r/w) table 42. bit descriptions for lim_right_ctrl3 bits bit name settings description reset access [7:0] vbat_inf_r right limiter batt ery voltage inflection point 0x22 r/w address: 0x14, reset: 0xff, name: clip_left_ctrl left dac high frequency clip value 0x00: clip to 1/256. 0xfc: ... 0xfd: clip to 254/256. 0xfe: clip to 255/256. 0xff: clip to 0 db. 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 [7:0] dac_clip_l (r/w ) table 43. bit descriptions for clip_left_ctrl bits bit name settings description reset access [7:0] dac_clip_l left dac high frequency clip value 0xff r/w 0xff clip to 0 db 0xfe clip to 255/256 0xfd clip to 254/256 0xfc 0x00 clip to 1/256
SSM3582 data sheet rev. 0| page 52 of 59 address: 0x15, reset: 0xff, name: clip_right_ctrl right dac high frequency clip value 0x00: clip to 1/256. 0xfc: ... 0xfd: clip to 254/256. 0xfe: clip to 255/256. 0xff: clip to 0 db. 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 [7:0] dac_clip_r (r/w ) table 44. bit descriptions for clip_right_ctrl bits bit name settings description reset access [7:0] dac_clip_r right dac high frequency clip value 0xff r/w 0xff clip to 0 db 0xfe clip to 255/256 0xfd clip to 254/256 0xfc 0x00 clip to 1/256 address: 0x16, reset: 0x00, name: fault_ctrl1 left channel over temperature warning gain reduction 11: 5.625 db gain reduction. 10: 3 db gain reduction. 1: 1.5 db gain reduction. 0: no gain reduction. right channel over temperature warning gain reduction 11: 5.625 db gain reduction. 10: 3 db gain reduction. 1: 1.5 db gain reduction. 0: no gain reduction. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:6] reserved [1:0] otw_gain_l (r/w) [5:4] otw _gain_r (r/w ) [3:2] reserved table 45. bit descriptions for fault_ctrl1 bits bit name settings description reset access [7:6] reserved reserved 0x0 r [5:4] otw_gain_r right channel over te mperature warning gain reduction 0x0 r/w 0 no gain reduction 1 1.5 db gain reduction 10 3 db gain reduction 11 5.625 db gain reduction [3:2] reserved reserved 0x0 r [1:0] otw_gain_l left channel over temperature warning gain reduction 0x0 r/w 0 no gain reduction 1 1.5 db gain reduction 10 3 db gain reduction 11 5.625 db gain reduction
data sheet SSM3582 rev. 0| page 53 of 59 address: 0x17, reset: 0x30, name: fault_ctrl2 engage manual fault recovery attempt 1: one manual recovery attempt. 0: no manual recovery attempt. overcurrent fault auto recovery control 1: manual recovery using mrcv bit. 0: auto recovery enabled. over temperature fault auto recovery control 1: manual recovery using mrcv bit. 0: auto recovery enabled. maxim um autom atic recovery attem pts 11: unlimited attempts. 10: 7 attempts. 1: 3 attempts. 0: 1 attempt. undervoltage fault auto recovery control 1: manual recovery using mrcv bit. 0: auto recovery enabled. 0 0 1 0 2 0 3 0 4 1 5 1 6 0 7 0 [7] mrcv (w ) [0] arcv_oc (r/w ) [6] reserved [1] arcv_ot (r/w) [5:4] max_ar (r/w) [2] arcv_uv (r/w ) [3] reserved table 46. bit descriptions for fault_ctrl2 bits bit name settings description reset access 7 mrcv engage manual fault recovery attempt 0x0 w 6 reserved reserved 0x0 r [5:4] max_ar maximum automatic recovery attempts 0x3 r/w 0 1 attempt 1 3 attempts 10 7 attempts 11 unlimited attempts 3 reserved reserved 0x0 r 2 arcv_uv undervoltage fault automatic recovery control 0x0 r/w 0 automatic recovery enabled 1 manual recovery using mrcv register 1 arcv_ot over temperature fault automatic recovery control 0x0 r/w 0 automatic recovery enabled 1 manual recovery using mrcv bit 0 arcv_oc over current fault automatic recovery control 0x0 r/w 0 automatic recovery enabled 1 manual recovery using mrcv bit
SSM3582 data sheet rev. 0| page 54 of 59 address: 0x18, reset: 0x00, name: status1 pvdd under-voltage fault condition 1: pvdd undervoltage fault condition. 0: pvdd ok. over temperature warning condition 1: over temperature warning. 0: no over temperature warning. regulator under-voltage fault condition 1: undervoltage fault for avdd regulator. 0: no undervoltage fault for avdd regulator. over temperature fault condition 1: over temperature fault. 0: no over temperature fault. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7] uvlo_pvdd (r) [0] otw (r) [6] uvlo_vreg (r) [1] otf (r) [5:2] reserved table 47. bit descriptions for status1 bits bit name settings description reset access 7 uvlo_pvdd pvdd undervoltage fault condition 0x0 r 0 pvdd ok 1 pvdd undervoltage fault condition 6 uvlo_vreg regulator undervoltage fault condition 0x0 r 0 no undervoltage fault for avdd regulator 1 undervoltage fault for avdd regulator [5:2] reserved reserved 0x0 r 1 otf over temperature fault condition 0x0 r 0 no overtemperature fault 1 overtemperature fault 0 otw over temperature warning condition 0x0 r 0 no overtemperature warning 1 overtemperature warning address: 0x19, reset: 0x00, name: status2 right limiter gain reduction engaged 1: lim iter gain reduction right on. 0: lim iter gain reduction right off. battery voltage warning for left channel (vbat vbat_inf_l left channel. right channel dac clipping detected 1: clipping right channel. 0: no clipping right channel. left channel amplifier overcurrent condition 1: over current left channel. 0: no over current left channel. right channel amplifier overcurrent condition 1: over current right channel. 0: no over current right channel. left channel dac clipping detected 1: clipping left channel. 0: no clipping left channel. battery voltage warning for right channel (vbat vbat_inf_r right channel. left limiter gain reduction engaged 1: limiter gain reduction left on. 0: lim iter gain reduction left off. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7] lim_eg_r (r) [0] bat_warn_l (r) [6] clip_r (r) [1] amp_oc_l (r) [5] amp_oc_r (r) [2] clip_l (r) [4] bat_warn_r (r) [3] lim_eg_l (r) table 48. bit descriptions for status2 bits bit name settings description reset access 7 lim_eg_r right limiter ga in reduction engaged 0x0 r 0 limiter gain reduction right off. 1 limiter gain reduction right on.
data sheet SSM3582 rev. 0| page 55 of 59 bits bit name settings description reset access 6 clip_r right channel dac clipping detected 0x0 r 0 no clipping right channel. 1 clipping right channel. 5 amp_oc_r right channel amplifier overcurrent condition 0x0 r 0 no overcurrent right channel. 1 overcurrent right channel. 4 bat_warn_r battery voltage warning for right channel (vbat < vbat_inf_x) 0x0 r 0 vbat > vbat_inf_r right channel. 1 vbat < vbat_inf_r right channel. 3 lim_eg_l left limiter ga in reduction engaged 0x0 r 0 limiter gain reduction left off. 1 limiter gain reduction left on. 2 clip_l left channel dac clipping detected 0x0 r 0 no clipping left channel. 1 clipping left channel. 1 amp_oc_l left channel amplifier overcurrent condition 0x0 r 0 no over current left channel. 1 over current left channel. 0 bat_warn_l battery voltage warning for left channel (vbat < vbat_inf_x) 0x0 r 0 vbat > vbat_inf_l left channel. 1 vbat < vbat_inf_l left channel. address: 0x1a, reset: 0x00, name: vbat battery voltage readback 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] vbat (r) table 49. bit descriptions for vbat bits bit name settings description reset access [7:0] vbat battery voltage readback 0x0 r address: 0x1b, reset: 0x00, name: temp temperature sensor readout 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:0] temp (r) table 50. bit descriptions for temp bits bit name settings description reset access [7:0] temp temperature sensor readout. the actual te mperature in degrees celsius is temp C 60 decimal. 0x0 r
SSM3582 data sheet rev. 0| page 56 of 59 address: 0x1c, reset: 0x00, name: soft_reset full software reset 1: perform full s oftware res et. 0: normal operation. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:1] reserved [0] s_rst (w) table 51. bit descriptions for soft_reset bits bit name settings description reset access [7:1] reserved reserved 0x0 r 0 s_rst full software reset 0x0 w 0 normal operation 1 perform full software reset
data sheet SSM3582 rev. 0| page 57 of 59 typical application circuit figure 86 shows a typical application circuit for a stereo output. figure 87 shows a typical application circuit for a mono out put. volume dac - ? class-d modulator volume dac - ? class-d modulator bclk fsync sdata outl+ outl? addr0 see device address setting section addr1 dvdd dvdd_en agnd pvdd pvdd pgnd scl sda i 2 c i 2 c tdm i 2 s input full bridge power stage bstl? bstr? bstl+ SSM3582 +1.8v +1.8v (dvdd) i 2 s/tdm pvdd r1 2.2k ? r2 2.2k ? 47k ? 47k ? c3 10f c2 10f c10 0.22f c11 0.22f c15 220pf c14 220pf +4.5v to +16v pvdd 4 ? /8 ? 4 ? /8 ? fb1 fb2 optional fb1/fb2: murata ferrite bead nfz2msm181 optional fb3/fb3: murata ferrite bead nfz2msm181 c9 470f c5 10f c4 0.1f reg dvdd reg avdd c7 10f c6 0.1f c8 470f outr+ outr? open addrx addrx addrx addrx addrx addrx pin setup options dvdd_en pin setup options gnd dvdd dvdd dvdd 47k ? to gnd 47k? to dvdd full bridge power stage bstr+ c12 0.22f c13 0.22f c16 220pf c17 220pf fb3 fb4 c1 0.1uf 13399-084 avdd avdd_en dvdd_en dvdd_en avdd avdd_en pin setup options avdd_en avdd_en pvdd figure 86. typical application circuit for stereo output
SSM3582 data sheet rev. 0| page 58 of 59 addr0 see device address setting section addr1 dvdd dvdd_en pvdd i 2 c +1.8v (dvdd) pvdd c3 10f c2 10f +4.5v to +16v pvdd c9 470f c5 10f c4 0.1f reg dvdd reg avdd c7 10f c6 0.1f c8 470f c1 0.1uf avdd avdd_en bclk fsync sdata agnd pvdd pgnd scl sda i 2 c tdm i 2 s input volume dac full bridge power stage - ? class-d modulator bstl? bstr? bstl+ SSM3582 +1.8v i 2 s/tdm r1 2.2k ? r2 2.2k ? c10 0.22f c11 0.22f c15 220pf c14 220pf 2 ? /3 ? fb1 fb2 optional fb1/fb2: murata ferrite bead nfz2msm181 volume dac full bridge power stage - ? class-d modulator bstr+ c12 0.22f c13 0.22f 13399-085 outl+ outl? outr+ outr? addrx pin setup options avdd pvdd dvdd_en pin setup options dvdd_en dvdd_en avdd_en pin setup options avdd_en avdd_en 47k ? 47k ? open addrx addrx addrx addrx addrx gnd dvdd dvdd dvdd 47k ? to gnd 47k ? to dvdd figure 87. typical application circuit for mono output
data sheet SSM3582 rev. 0| page 59 of 59 outline dimensions 06-04-2012-a 0.50 bsc bottom view top view pin 1 indicator exposed pad p i n 1 i n d i c a t o r seating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 6.10 6.00 sq 5.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.45 0.40 0.35 0.20 min * 4.70 4.60 sq 4.50 *compliant to jedec standards mo-220-wjjd-5 with exception to exposed pad dimension. 40 1 11 10 20 21 30 31 figure 88. 40-lead lead free chip scale package [lfcsp] 6 mm 6 mm body and 0.75 mm package height (cp-40-7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option SSM3582bcpz ?40c to +85c 40-lead lead free chip scale package [lfcsp] cp-40-7 SSM3582bcpzrl ?40c to +85c 40-lead lead free chip scale package [lfcsp] cp-40-7 SSM3582bcpzr7 ?40c to +85c 40-lead lead free chip scale package [lfcsp] cp-40-7 eval-SSM3582z evaluation board 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d13399-0-4/16(0)

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